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Error Correction Circuitry for Dynamic Random Access Memories

IP.com Disclosure Number: IPCOM000105687D
Original Publication Date: 1993-Aug-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Dvorak, TJ: AUTHOR [+3]

Abstract

Described is a hardware implementation for personal computer (PC) systems to provide error correction circuitry (ECC) for dynamic random access memories (DRAMs). The design enables 36-bit wide memory modules to be used eliminating the need to replace it for a 40-bit wide module.

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Error Correction Circuitry for Dynamic Random Access Memories

      Described is a hardware implementation for personal computer
(PC) systems to provide error correction circuitry (ECC) for dynamic
random access memories (DRAMs).  The design enables 36-bit wide
memory modules to be used eliminating the need to replace it for a
40-bit wide module.

      PCs utilize multiple circuit boards that plug into a base
planar, such as a processor circuit card and memory circuit modules
along with input/output (I/O) connectors.  Typically, the processor
circuit card includes a microprocessor, a memory controller, a cache
controller, clocking controls and associated logic to interconnect to
functional units of a system.  Memory modules generally contain
memory words that are 32-bits wide and have a parity bit for each
eight bits to provide a total word width for a parity system of
36-bits.  To add ECC capability for a single bit correction and a
double bit detection requires a data word that is 39-bits wide.  In
prior art, the 36-bit memory module array with parity was replaced
with a 40-bit wide array module so as to provide ECC capability.

      The concept described herein eliminates the need to replace the
existing 36-bit memory module array by placing an ECC module
logically between the processor card and the planar.  Fig. 1 shows
the mechanical configuration of positioning the ECC module in
relation to the processor and memory modules on the planar board and
Fig. 2 shows the logical architecture involved for adding the ECC
module to the circuitry.  The ECC module is located between the
processor and the memory module, as shown in Fig. 1, and contains...