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DRAM Reference Scheme for Optimized Signal Margin

IP.com Disclosure Number: IPCOM000105701D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Barth, JE: AUTHOR

Abstract

A DRAM reference scheme is described that can be designed to favor one desired data state over the other to compensate for asymmetric DRAM leakage mechanisms. Specially designed reference wordline drivers use charge sharing to set both wordline outputs at VDD/2 to disable writeback. RAS initiates writeback for a fixed duration by driving both reference wordline outputs to ground. This technique offers the advantages of fixed duration writeback to reduce the effects of cycle-dependent noise without wordline boosting.

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DRAM Reference Scheme for Optimized Signal Margin

      A DRAM reference scheme is described that can be designed to
favor one desired data state over the other to compensate for
asymmetric DRAM leakage mechanisms.  Specially designed reference
wordline drivers use charge sharing to set both wordline outputs at
VDD/2 to disable writeback.  RAS initiates writeback for a fixed
duration by driving both reference wordline outputs to ground.  This
technique offers the advantages of fixed duration writeback to reduce
the effects of cycle-dependent noise without wordline boosting.

      During the read portion of the cycle, both array and
corresponding reference wordlines are selected.  After data is sensed
and amplified, the shared common node (RWLCOM in Fig. 1) of reference
wordline drivers I0 and I1 is floated and the unselected reference
wordline is activated.  The activation initiates charge sharing
between the selected and unselected wordlines, resulting in both
reference wordlines going to VDD/2.  With the reference wordlines at
VDD/2, full signal writeback is disabled until restore.  When restore
is initiated by RAS as shown in Fig. 2, node RWLCOM is pulled from
VDD/2 back to ground.  Both REFWL0 and REFWL1 fall to ground and
writeback begins for a fixed time duration.  When the fixed writeback
time is complete, both the array wordline and the reference wordlines
are shut off.

      While the particular implementation shown in Fig. 1 favors the
logic...