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Browse Prior Art Database

Concurrent Operation of Local and Micro Channel Busses

IP.com Disclosure Number: IPCOM000105752D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 79K

Publishing Venue

IBM

Related People

Baker, R: AUTHOR [+6]

Abstract

Disclosed is an enhancement to the local bus architecture to allow concurrent operation of the local and Micro Channel* busses under certain conditions. The nature of traffic initiated by the local bus master devices is determined and made available to the local bus arbiter, and traffic on the local bus, not requiring the use of the Micro Channel bus, is allowed when the Micro Channel bus is engaged in a burst transfer not requiring the use of the local bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Concurrent Operation of Local and Micro Channel Busses

      Disclosed is an enhancement to the local bus architecture to
allow concurrent operation of the local and Micro Channel* busses
under certain conditions.  The nature of traffic initiated by the
local bus master devices is determined and made available to the
local bus arbiter, and traffic on the local bus, not requiring the
use of the Micro Channel bus, is allowed when the Micro Channel bus
is engaged in a burst transfer not requiring the use of the local
bus.

      As shown in the figure, a computer system includes a local bus
1, to which various local devices, such as a processor 2, a
coprocessor 3, a SCSI controller 4, a digital signal processor 5, and
a video controller 6, are directly connected.  The system also
includes a Micro Channel bus 7, to which various external devices
(not shown) are connected.  Local bus 1 provides high-speed data
transfer because it is synchronous and because its arbitration
overhead is low.  A Bus Interface Chip (BIC) 8 provides local and
Micro Channel arbitrations, allowing local and Micro Channel bus
traffic to occur simultaneously when all of the following conditions
are met:

 1.  A Micro Channel bus master, i.e., an external device, has
    control over the Micro Channel bus.

 2.  The external device does not access any of the resources
    residing on the local bus.

 3.  The external device does a burst transfer.  Preferably, to
    optimize system performance, in the event that the external bus
    master crosses the local address boundary, the Local bus
    arbiter returns a "not ready" signal while forcing the local
    device off the local bus.

 4.  There is at least one local device, i.e., a device connected to
    the local bus, which requests transfers with local destination
    addresses.  Other local devices, with external destination
    addresses, must temporarily yield to local devices with local
    destination addresses.

      To determine whether the first of these conditions is met,
circuits within the bus interface chi...