Browse Prior Art Database

Integrated Attachment for Small Gap CKD DASD

IP.com Disclosure Number: IPCOM000105760D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 112K

Publishing Venue

IBM

Related People

Findlay, RG: AUTHOR [+2]

Abstract

A block diagram of such an integrated attachment is shown in the figure. It consists of a microprocessor 5 and its control store (CS) 10, a device adapter (DA) 15 for attaching to disks, a data buffer 20 through which data is staged when it is moved between the host system and the disks, and a system adapter 25 for communicating with the system.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Integrated Attachment for Small Gap CKD DASD

      A block diagram of such an integrated attachment is shown in
the figure.  It consists of a microprocessor 5 and its control store
(CS) 10, a device adapter (DA) 15 for attaching to disks, a data
buffer 20 through which data is staged when it is moved between the
host system and the disks, and a system adapter 25 for communicating
with the system.

      The system adapter (SA) is shown in great detail in the figure,
since it contains the new features of the disclosed attachment
subsystem.  Between the microprocessor and the SA, there is 32-bit
data bus 30, a 6-bit address bus 35, and separate Read 40, Write 45,
and chip select 50 lines.  The six bits of address are used to
address the 32 26-bit association registers 55 shown in the SA, and
also the four other registers shown separately (the command register
60, the host address register 65, the Test Host Address Register 70,
and the Test Result Register 75).  The SA also contains other
registers which are not shown, since they are fairly standard and do
not add to the description of the disclosed attachment subsystem.

      For this implementation, assume that host addresses are 24 bits
(as in System/370).  Since a CCW is 8 bytes, the last three bits of
the 24-bit host address must be zeroes, so that the host address of a
CCW may be represented as a 21-bit quantity by shifting the host
address to the right by 3 bits.  Shown also is a 256-byte CCW store
80 in the SA which may contain as many as 32 CWs.  The CCW store can
be addressed with 8 bits, but 5 bits are sufficient to represent the
location where a CCW begins, since it must begin on an 8-byte
boundary.

      Each 26-bit register really consists of two parts--a 21-bit
host address and a 5-bit CCW store address.  If a CCW from host
address H is stored in the CCW store at location Y, one of the 32
26-bit registers will contain H shifted right by three bits in the
first 21 bits and Y shifted right by 3 bits in the last 5 bits.
Thus, this register maintains the association between location H in
host memory and location Y in CCW store memory.  In general, the 32
association registers maintain the host memory to CCW store memory
association for each of the 32 CCWs in the CCW store.  For each of
the 32 association registers, there is a 21-bit comparator 85.  These
32 comparators are used in parallel to compare a given 21-bit host
address with each of the 21-bit host addresses in the 32 association
registers.  The equal outputs from the 32 comparators are ORed to
drive the chip select line of the CCW store.  The equal outputs from
each of the comparators are also used to gate a 5-bit CCW store
address from one of the 32 association registers.  The host...