Browse Prior Art Database

Controlling Computer Processor Initialization

IP.com Disclosure Number: IPCOM000105763D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 169K

Publishing Venue

IBM

Related People

Bustamante, C: AUTHOR [+2]

Abstract

Described is hardware circuit implementation to provide control over processor operation during initialization power-up routines. The design centers about the oscillator design of certain computer central processing units (CPUs), such as the i486*. Discussed are several solutions and combinations to overcome problem areas.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 33% of the total text.

Controlling Computer Processor Initialization

      Described is hardware circuit implementation to provide control
over processor operation during initialization power-up routines.
The design centers about the oscillator design of certain computer
central processing units (CPUs), such as the i486*.  Discussed are
several solutions and combinations to overcome problem areas.

      The concept of controlling computer processor initialization
was prompted as a result of an industry manufacturer's Errata Sheet*.
The problem essentially involves a hang-up during power-up time where
the oscillator turns on before reaching the required voltage.  It has
been determined that additional problems can occur with processors
which contain phase-locked loops (PLLs).

      The circuit design described herein implements a control
embodiment to solve the problems outlined above.  Fig. 1 shows a
block diagram of the system embodiment.  The i486 - 50 MHz processor
10 has an internal clock generation circuit PLL unit 11 to reduce the
oscillator frequencies.  Since it has been determined that the i486
internal PLL will lock to a harmonic of the intended frequency, this
harmonic lock is a perfectly stable state, as seen in this problem.

Square-wave inputs to PLLs are considered the worst case since they
contain high odd harmonic energy.  Temperature and supply voltages
also play a role in the problem since the PLL parameters depend on
them.  Loop filter bandwidth, VCO gain and phase detector
characteristics of the i486 internal PLL lock to an incorrect
frequency when the supply voltage is under four volts and the
temperature is near 85ºC or above.

      Power supply 12 increases the voltage slowly at power-on to
charge all of the capacitances in the system and to energize the DC
motors, while not going into an over-current condition.  Power supply
12 is rated to produce a system supply voltage +/- a specific
tolerance.  The amount of time it takes the power supply to reach the
rated voltage within its tolerance varies with the number of features
in the system.  The power supply generates a power_good signal which
indicates specified supply voltage levels.  The power_good signal
goes to its active state when the power supply voltage level reaches
4.75V.

      System oscillator circuit 13 runs at 50 MHz and is typically a
metal can type common in most designs.  It has a total of four pins,
one being the control pin or the enable pin.  The design uses this
pin as an input and a means of controlling when the system "sees" the
oscillator.

      System synchronous reset logic unit 14 contains the logic
responsible for resetting the processor.  The processor will be
activated when power_good goes active and is implemented as
synchronous logic, synchronous to the system oscillator.  The
oscillator is enabled prior to the power_good signal so that the
system reset logic is alive and must be enabled prior to the reset
signal to...