Browse Prior Art Database

Generation of Extended Processor Identification Bits

IP.com Disclosure Number: IPCOM000105764D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Capps Jr, LB: AUTHOR [+8]

Abstract

Disclosed is a method for generating additional bits to be sent to an I/O port register for extending the possibilities of identification of the processor module within a computer. Such identification bits can be used, for example, to identify the type of processor module and the speed at which it is designed to operate.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 74% of the total text.

Generation of Extended Processor Identification Bits

      Disclosed is a method for generating additional bits to be sent
to an I/O port register for extending the possibilities of
identification of the processor module within a computer.  Such
identification bits can be used, for example, to identify the type of
processor module and the speed at which it is designed to operate.

      As shown in the figure, the processor identification bits are
determined from the combination of jumpers (zero-ohm resistors) 10
which are present or absent in the inputs to four gate circuits
12a-12d.  Each of these inputs is also tied to +5 volts through a
10K-ohm pull-up resistor 14.  Thus, when a jumper 10 is present, the
input to the associated gate circuit 12a-12d is at a logic level
zero, while the absence of the jumper 10 results in an input at a
logic level one.  Each gate circuit 12A-12d produces an output
corresponding to its input when a signal is present on its ENABLE
line.

      The signals to these ENABLE lines are generated from the Bit 3
output of PORT E3 register 16.  When PORT E3 Bit 3 is at a one level,
gate circuit 12a is enabled so that its output is provided as a Bit 2
input to PORT E2 register 18, and gate circuit 12b is enabled so that
its output is provided as a Bit 6 input to PORT E2 register 20.  The
Bit 3 output of register 16 is inverted by inverter circuit 22, to
provide ENABLE inputs to gate circuits 12c and 12d.  When PORT E3 Bit
3 input i...