Browse Prior Art Database

Dual-Speed Memory Controller

IP.com Disclosure Number: IPCOM000105770D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 95K

Publishing Venue

IBM

Related People

Aldereguia, A: AUTHOR [+5]

Abstract

Disclosed is a dual-bus memory controller interfacing to planar memory at full speed for all processor accesses and at half speed for DMA (Direct Memory Access) accesses, which do not involve the processor. On the system bus, the memory controller communicates with the DMA controller at half speed, and with the BIU (Bus Interface Unit) controller at full speed. Thus, a relatively inexpensive, lower-speed technology can be used in the DMA controller without degrading the performance of the system during processor memory accesses. Furthermore, during a DMA memory access cycle, the portions of the cycle controlled by the memory controller sequencer occur at full speed, while the DMA controller runs at half speed.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Dual-Speed Memory Controller

      Disclosed is a dual-bus memory controller interfacing to planar
memory at full speed for all processor accesses and at half speed for
DMA (Direct Memory Access) accesses, which do not involve the
processor.  On the system bus, the memory controller communicates
with the DMA controller at half speed, and with the BIU (Bus
Interface Unit) controller at full speed.  Thus, a relatively
inexpensive, lower-speed technology can be used in the DMA controller
without degrading the performance of the system during processor
memory accesses.  Furthermore, during a DMA memory access cycle, the
portions of the cycle controlled by the memory controller sequencer
occur at full speed, while the DMA controller runs at half speed.  A
full-speed clock signal, FULL_CLK, is provided to the memory
controller at, for example, 40 MHz, along with a half=speed clock
signal, HALF_CLK, synchronized with the full-speed clock signal.

      Figure 1 provides a timing chart showing the operation of the
memory controller at full speed, in a packet read, page miss,
processor access to memory.  The timing conditions of the various
portions of this cycle are established by the physical
characteristics of the circuits, with events occurring as rapidly as
they can be expected to occur reliably, within the constraint
provided by the resolution of the full-speed clock at 40 MHz.

      This access cycle is begun with the SADS (System Address Data
Strobe) signal, which occurs in a single clock cycle.  Next, the RAS
(Row Address Select) signal is driven active for three clock cycles.
Following a delay of two clock cycles, the CAS (Column Address
Select) signal is driven active for four clock cycles.  Next, the
SBRDY signal, which occurs with the end of each access cycle, is
driven active for two clock cycles.  During the first of these clock
cycles, the first 32-bit double word is read, and during the second
of these clock cycles, the second double word is read.  CAS is also
precharged during these two clock cycles.  Next, CAS is again driven
active for four clock cycles, after which the SBRDY signal is again
driven active for two clock cycles.  During the first of these, the
third double word is read, and during the second of these, the fourth
double word is read.

      Thus, the reading of the first double word is completed after
eleven clock cycles, the reading of the second double word is
completed after one additional clock cycle, the reading of the third
double word is completed after five addit...