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Memory Configuration Table

IP.com Disclosure Number: IPCOM000105782D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 115K

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Related People

Fuoco, DP: AUTHOR [+3]


This article describes a technique which uses a table to actuate the correct bank of memory in a computer memory controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Memory Configuration Table

      This article describes a technique which uses a table to
actuate the correct bank of memory in a computer memory controller.

      The memory controller is able to handle a wide variety of
memory configurations.  A programmable table is used to specify the
memory configuration to the controller.  The technique used is to
divide the memory address space into segments and assign an attribute
to each segment.  The attributes are stored in a table.  Each table
entry corresponds to a segment.  In the implementation described,
segment sizes are 1MB within a 16MB address range.  Thus, there are
sixteen entries in the table.  Other segment sizes and address ranges
could be accommodated by this same method.

      The contents of the table describe the memory configuration.
Therefore, by simply loading the table with the corresponding
attributes for the installed memory, the memory controller hardware
automatically adjusts its memory address decodes to match.

      An entry in the table is selected by segment number.  The entry
contents define which set of control signals must be generated for
the address.  The segment number corresponds to the most significant
part of the address.  Therefore, to uniquely select the appropriate
set for control signals, only a one step lookup is required.  Prior
methods decode addresses with comparators which are multilevel logic
structures that add considerable delay to the access time.

      In the drawings the table of Fig. 2 is referred to as the row
address strobe (RAS) table.  Fig. 1 defines the structure of the bus
interface chip (BIC) RAS table entries.  The processor support chip
PSC RAS table has thirty-two entries.  Each entry corresponds to
512KB.  The BIC RAS table is sixteen entries.  Each entry corresponds
to 1MB.

      The BIC chip memory controller has two registers that are
programmed by power-on-self-test (POST) code to set the configuration
and the operating mode of the memory controller.  Each of these
registers is 8 bits wide.  These registers are located at addresses
E0h.  E1h.

      There are three slots to install up to three memory single
inline memory modules (SIMMs) on the planar.  Each memory SIMM has
one or two banks.  Each bank of memory is addressed by a different
RAS line.  RAS0 and RAS1 are used to access the first SIMM.  RAS2 and
RAS3 are used to access the second SIMM.  RAS4 and RAS5 are used to
access the third SIMM.

      Ports E0h and E1h (RAS Table):  The RAS table contains the
translation of the physical address to the actual SIMM address,
RAS(0..5), the size of the memory bank, and the split address
information.  Sixteen 8-bit registers for one of the 16...