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Improved Edge Detection Circuit

IP.com Disclosure Number: IPCOM000105829D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Butler, E: AUTHOR [+3]

Abstract

The rising edge detection circuit of Fig. 1 generates a low output pulse of known duration whenever the digital input signal rises from a low level to a high level. The falling edge detection circuit of Fig. 2 generates a high output pulse of known duration whenever the digital input signal falls from a high level to a low level. Previous edge detectors required that the width of the input pulse to be detected must be at least as long as the circuit path delay prior to the final gate. The modified edge detection circuits described below require only that the width of the input pulse to be detected must exceed the circuit path delay through the first two inverters. It is assumed that the period between input pulses is longer than the circuit path delay prior to the final gate.

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Improved Edge Detection Circuit

      The rising edge detection circuit of Fig. 1 generates a low
output pulse of known duration whenever the digital input signal
rises from a low level to a high level.  The falling edge detection
circuit of Fig. 2 generates a high output pulse of known duration
whenever the digital input signal falls from a high level to a low
level.  Previous edge detectors required that the width of the input
pulse to be detected must be at least as long as the circuit path
delay prior to the final gate.  The modified edge detection circuits
described below require only that the width of the input pulse to be
detected must exceed the circuit path delay through the first two
inverters.  It is assumed that the period between input pulses is
longer than the circuit path delay prior to the final gate.

      The rising edge detector of Fig. 1 differs from previous edge
detectors by using NAND gates A1 and A2 in place of inverters.  If
only inverters are used, the pulse width at terminal IN must be at
least as long as the circuit delay through the inverters, or five
gate delays in the case of Fig. 1.  Otherwise, the output pulse width
will be diminished.  A1 assures satisfactory operation as long as IN
is at a low level for at least the delay time through inverters I1
and I2, which is only two gate delays.  This concept holds for any
odd number of gates in the delay path as long as all odd-numbered
gates after the first one are NAND gates with...