Browse Prior Art Database

Efficient Streaming Data Bus

IP.com Disclosure Number: IPCOM000105830D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 6 page(s) / 227K

Publishing Venue

IBM

Related People

MacInnis, AG: AUTHOR

Abstract

Disclosed is a data bus design which is extremely efficient in terms of pins and which provides all of the functions needed in many bus designs while providing high performance for streaming or burst-oriented data transfers.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 24% of the total text.

Efficient Streaming Data Bus

      Disclosed is a data bus design which is extremely efficient in
terms of pins and which provides all of the functions needed in many
bus designs while providing high performance for streaming or
burst-oriented data transfers.

The streaming data bus has the following characteristics:

1.  Clock synchronous; provides speed, reliability and ease of
    design.

2.  Multiplexed control and data, where control includes address
    information.

3.  Latch-to-latch timing (maximum speed for the bus technology
    used).

4.  Basic design has 32 data lines, three control lines and one clock
    line; minimum number of pins for the function.  Plug-compatible
    devices of lesser and greater widths are supported (e.g., 16 or
    64 data lines).

5.  Bidirectional, single-word, pipelined pacing (source and
    destination).

6.  Bidirectional data transfers (masters to/from slaves).

7.  Multimaster, multislave operation.

8.  Token passing arbitration with no additional pins.  The bus line
    definitions are:

    a.  DATA(0 - 31):  bidirectional data, also used for control
        information and passing arbitration tokens.

    b.  CLOCK:  continuously running master clock, driven from a
        single point.  Input to all master and slave logic.

    c.  DATA/-CTL:  driven by the active master; indicates whether
        data being written over the bus are control fields or data.

    d.  -MASTERRDY:  driven active by the active master to indicate
        that it is presenting valid data during a write transfer, or
        that it is ready to accept data during a read transfer.

    e.  -SLAVERDY:  driven active by the active slave to indicate
        that it is ready to accept data during a write transfer, or
        that it is presenting valid data during a read transfer.

      Devices on the bus can be masters, slaves or both.  Masters are
devices that arbitrate for the bus and initiate transfers by
addressing slaves.  Data can flow in either direction between a
master and a slave.  A device that is a slave during one transfer can
be a master in a subsequent transfer, and vice versa.

Operations - Write Transfer

1.  When no transfer is in progress, -MasterRdy and -SlaveRdy are
    inactive (high).

2.  The previous active master passes control of the bus to the next
    master by transmitting the arbitration token on the data lines to
    the next master.  The token is one of a reserved set of values on
    the Data() lines while Data/-Ctl is low (i.e., a special control
    field).  The previous master transmits the arbitration token by
    driving both -MasterRdy and Data/-Ctl low along with the token
    value on the Data() lines.  The next master receives the
    arbitration token by noting the 'Next Master' subfield in the
    Arbitration Token control field being equal...