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Deriving a Distributed Memory Model from a Shared Memory Model

IP.com Disclosure Number: IPCOM000105838D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 165K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+2]

Abstract

There are two distinct types of parallelism which can be categorized as Coarse Grained (CG) parallelism and Fine Grained (FG) parallelism. Fine-grained parallelism operates on the instruction level and partitions a putative instruction stream that has a single logical register file and a single memory hierarchy among several processor elements. As such, fine-grained parallelism allows successive instructions to be executed in parallel and requires that the result of such executions conform to a RUBRIC OF SEQUENTIAL CORRECTNESS. Another implication of this is that the memory hierarchy that supports fine-grained parallelism is common to all processor elements that share the same putative instruction stream.

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Deriving a Distributed Memory Model from a Shared Memory Model

      There are two distinct types of parallelism which can be
categorized as Coarse Grained (CG) parallelism and Fine Grained (FG)
parallelism.  Fine-grained parallelism operates on the instruction
level and partitions a putative instruction stream that has a single
logical register file and a single memory hierarchy among several
processor elements.  As such, fine-grained parallelism allows
successive instructions to be executed in parallel and requires that
the result of such executions conform to a RUBRIC OF SEQUENTIAL
CORRECTNESS.  Another implication of this is that the memory
hierarchy that supports fine-grained parallelism is common to all
processor elements that share the same putative instruction stream.

      The basic computational entity within coarse-grained
parallelism is a THREAD which is given a name.  Each THREAD is said
to comprise a sequence of steps (beads) which are one of the
following types:

1.  COMPUTE STEP (USING LOCAL MEMORY/REGISTERS)

2.  CONDITIONAL FORK AND THREAD(NAME) CREATION

3.  SEND BUFFER TO NAME

4.  WAIT & RECEIVE BUFFER

These threads are called CSR because of the compute-send-receive
aspect of their structure.  The definition of the COMPUTE-STEP
involves a long sequence of instructions that operate within the
context of a local memory which is comprised of private registers and
a private memory hierarchy.  The operation of the SEND-BUFFER and
WAIT&RECEIVE-BUFFER is performed in conjunction with the local memory
associated with the named-THREAD and different named-THREADS can have
different templates for realizing the structure of the local memory
within the common hardware.  An important parameter of such
coarse-grained parallelism is the ratio of the COMPUTE-STEP time to
the SEND-BUFFER time.  Coarse-grained parallelism usually involves a
distributed memory system in which each CSR is supported by its own
private memory.

      The transformation of a computational paradigm that operates
with a shared memory into an equivalent computational paradigm  based
on distributed memory takes a sequential algorithm and creates a
parallel representation in terms of CSRs.  The means of accomplishing
this is described.  Given an algorithm that has been compiled as two
distinct program sections and processed on different sides of a
tightly coupled (shared memory) system, the cache misses within such
a system give telltale information about the needs of messages when
such sections are executed in a distributed memory system.  In order
to determine the exact needs of such a message traffic a timestamping
of lines accessed in the shared memory mode can classify accesses at
the granularity of cache lines into the following three classes;

o   lines that are shared but not changed,

o   lines that are not shared, and

o   lines which are shared and modified.

It is only the last category that created the annotations that
indicat...