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Generating Test Vectors for Very Large Scale Integration Devices

IP.com Disclosure Number: IPCOM000105839D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 64K

Publishing Venue

IBM

Related People

Becker, DO: AUTHOR [+2]

Abstract

Described is a software implementation for generating vectors used in the testing of very large-scale integration (VLSI) devices. The method is an improvement over conversion test vector methods in that test vectors are generated while simulation is being created.

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This is the abbreviated version, containing approximately 55% of the total text.

Generating Test Vectors for Very Large Scale Integration Devices

      Described is a software implementation for generating vectors
used in the testing of very large-scale integration (VLSI) devices.
The method is an improvement over conversion test vector methods in
that test vectors are generated while simulation is being created.

      In the prior art, test vector conversion programs were used to
process simulation files after they were created.  The concept
described herein provides a means of running the programs in the
simulation environment and to generate test vectors while the
simulation is being created.

      Typically, VLSI devices are designed and simulated in a
software environment using a basic design language structure (BDLS).
The VLSI logic is designed in the BDLS code and then compiled and
simulated for the device.  Test cases are run to exercise the design
so as to verify the proper function.  The simulator runs test cases
and generates logic states for each pin during the simulation run.
Conversion programs are used to change the generated logic states
into test vectors for the VLSI tester system.  Fig. 1 shows a block
diagram of the prior-art VLSI device test procedure.

      The concept described herein implements a testing method which
improves on the testing process by eliminating the conversion of the
simulated output process into test vectors.  The improved method,
called TEX, captures the simulation during the operation o...