Browse Prior Art Database

Command Sequencing for an Advanced Microcoded Rasterizer

IP.com Disclosure Number: IPCOM000105840D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 123K

Publishing Venue

IBM

Related People

Bowen, AD: AUTHOR [+4]

Abstract

A means for controlling the sequencing of a microcoded graphics processor is disclosed. The sequencing means allows for flexible functions based on per-pixel compare operations to be performed. Furthermore, efficient inner loops can be generated to allow for steady-state pipelining of the data through the modification logic.

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This is the abbreviated version, containing approximately 44% of the total text.

Command Sequencing for an Advanced Microcoded Rasterizer

      A means for controlling the sequencing of a microcoded graphics
processor is disclosed.  The sequencing means allows for flexible
functions based on per-pixel compare operations to be performed.
Furthermore, efficient inner loops can be generated to allow for
steady-state pipelining of the data through the modification logic.

      Most graphics pipelines consist of a geometry subsystem feeding
vertex information to a rasterization subsystem.  The rasterization
subsystem performs two functions.  First, it interpolates the
coordinates and vertex information for all points between the
vertices.  Second, it merges the interpolated pixel data (for
example, X, Y, Z, red, green, blue, alpha, fog, and a (u,v)
coordinate for texture) with the current image in the frame buffer.
The merging function may include comparisons between one or more X
values, blending the new BGR color with the old based on one or more
alpha coefficients, and other tests.  Most, if not all, rasterizers
have the various tests and blend operations specified in a static
fashion.  A command is generated that sets a bit to enable a given
test.  This approach has been improved upon by adding a simple
microcoded sequencer to the modification logic that allows the user
to specify a fixed sequence of operations, thereby allowing new
functions to be performed by combining simpler functions.  This
solution does not allow for the function to vary in a flexible manner
based on the result of the compare operations.  One example of where
this is useful is the polygon antialiasing algorithm defined in [*]
which specifies that one of three blend operations be performed based
on the Z-compare (greater-than, less-than, or equal).  Although this
particular function could be designed in to the silicon, it does not
address the general class of problems that have multiple processing
paths based on compare functions.

      The microcoded sequencer of the modification logic (hereinafter
referred to as "nanocode") consists of a very wide control word, or
"nanoword".  In the current implementation, the nanoword is 144 bits
wide and controls processing in modification units for color, Z,
alpha, stencil, utility, and window (scissoring).  The utility unit
is provided for miscellaneous functions and area fill control, and
comprises a per-bit controllable Boolean modification unit and an
8-bit comparator.

      In the current implementation, there are 6 comparators, five of
which are used to influence the sequencing of the nanocode.  The
color comparator is used only for hatch operations and 5080 support,
and does not influence the sequencer.  This decision was made based
on bit restrictions in the nanocode memory.  Of the remaining 5
compare results, 4 are used to control the sequencer in a flexible
way.  If the window test fails, the nanocode sequencer aborts the
current pixel by emptying out the input queu...