Browse Prior Art Database

Methods of Reducing the Worst Case Address Line Capacitance on a Memory Sub-System

IP.com Disclosure Number: IPCOM000105842D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Cipolla, TM: AUTHOR [+3]

Abstract

On a memory SIMM the worst-case address line capacitance and the variation between best and worst-case address line capacitance limit the performance of a memory sub-system or SIMM. This article describes methods for reducing the worst-case address line capacitance on a memory sub-system or SIMM. In this discussion we will talk to a memory SIMM; however, this discussion also applies to other memory sub-systems.

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Methods of Reducing the Worst Case Address Line Capacitance on a Memory Sub-System

      On a memory SIMM the worst-case address line capacitance and
the variation between best and worst-case address line capacitance
limit the performance of a memory sub-system or SIMM.  This article
describes methods for reducing the worst-case address line
capacitance on a memory sub-system or SIMM.  In this discussion we
will talk to a memory SIMM; however, this discussion also applies to
other memory sub-systems.

METHOD 1: GENERAL CASE

      This method reduces net capacitance on a memory SIMM by
allowing the SIMM manufacturer to connect address nets to different
address pins on different RAM modules.

      Presently, on a memory SIMM all A0 pins are dotted, all A1 pins
are dotted, and so on.  On a particular manufacturer's RAM, different
pins are likely to have different worst-case capacitance.  In most
cases, the address lines to a DRAM can be swapped without any effect.
(A case where swapping address lines would not be acceptable is a
DRAM that needs to be refreshed in a certain address order.)

      This method balances the address line capacitance on the SIMM
by wiring one address line on the SIMM to different pins on different
RAMs.  The manufacturer of the SIMM could be required to meet a lower
worst-case address net capacitance than could be met without this
method.

METHOD 2: SPECIFYING THE ADDRESS ORDERING

      In the previous method it was suggested that the SIMM
manufacturer wire address nets to different pins on the RAMs to
provide a lower worst-case capacitance.  However, the test mode on
DRAMs puts different functions on different DRAM address pins.  By
allowing each manufacturer to choose the wiring that it likes, test
mode could function differently on each SIMM.

      This method allows an address net to be wired to different RAMs
while allowing test mode to be useful.  This method requires
specifyi...