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Browse Prior Art Database

Overlapped Extended Graphic Adapter Block Transfer for Personal Computers

IP.com Disclosure Number: IPCOM000105851D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 134K

Publishing Venue

IBM

Related People

Cheung, ST: AUTHOR [+3]

Abstract

Described is an architectural implementation for personal computers (PCs) that are equipped with a Micro Channel* (MC)DOS. Instead of data bus sharing, this implementation offers improved performance by providing overlapped extended graphic adapter (XGA) block transfer operations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 44% of the total text.

Overlapped Extended Graphic Adapter Block Transfer for Personal Computers

      Described is an architectural implementation for personal
computers (PCs) that are equipped with a Micro Channel* (MC)DOS.
Instead of data bus sharing, this implementation offers improved
performance by providing overlapped extended graphic adapter (XGA)
block transfer operations.

      In prior art, XGA data flow operations required the sharing of
the same data bus that connected to the MC system bus, the MC
buffers, the XGA system bus interface (SBI) and the video
random-access memory (VRAM).  This sharing of the data bus prevented
XGA operations from accessing the MC until the data was written out
of the VRAM and caused inefficient data flow operations, resulting in
poor operational performance.

      Fig. 1 shows a block diagram of the prior-art interconnection
for the XGA data flow.  When the XGA acts as a busmaster, it would
preempt the MC bus and go into an arbitration cycle.  After the bus
was granted to the XGA, data transferred from the MC buffer to the
XGA-SBI.  When the XGA released the MC bus, the XGA-SBI data was
written to the VRAM.  It did not preempt the MC bus until the VRAM
write cycle was completed.  Fig. 2a shows a block diagram of the
prior art XGA data flow, and Fig. 2b shows the memory read cycle time
relationship of the prior-art concept.

      The improved concept described herein utilizes dual data buses
so as to provide an overlapped XGA block transfer of data.
Performance is enhanced by enabling a simultaneous flow of data.  The
first data bus continues to provide a path for data to flow between
the MC bus and the XGA-SBI.  The second data bus provides a
simultaneous flow of data between the XGA-SBI and the VRAM.  Fig. 3
shows a block diagram of the performance objectives, it is necessary
to provide a second first-in, first-out (FIFO) buffer within the
XGA-SBI.  Fig. 4a shows a block diagram of the XGA data flow
utilizing the buffer, and Fig. 4b shows the memory read cycle time
relationship of the improved XGA transfer.

      In actual operation, control logic will assert an input enable
(IE) signal (Fig. 4a) to one of the FIFO buffers so that data can be
loaded from the MC.  Simultaneously, an output enable (OE) signal
from the other FIFO buffer transfers data to the VRAM, if that FIFO
buffer is loaded with data.  Once the data is loaded from the MC and
data from the other output FIFO buffer is loaded to the VRAM, the
operation of the FIFO buffers can be reversed.  This allows an
overlapping of the data transfer operations.

      It is significant to note that the time required to output data
from a FIFO buffer to the VRAM is faster than the time required to
load data into a FIFO buffer.  This is because the time required for
the XGA memory controller to assert the column address strobe (CAS)
lines and the row address strobe (RAS) lines to the VRAM is faster
than the MC bus cycles when the c...