Browse Prior Art Database

Floating Point Adder for IEEE Floating Point Standard-754

IP.com Disclosure Number: IPCOM000105869D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 92K

Publishing Venue

IBM

Related People

Atkins, MG: AUTHOR

Abstract

The disclosed adder takes advantage of anticipate circuits. There is a parallel activity during the addition portion that takes advantage of characteristics of IEEE Floating Point Standard - 754. The resulting adder gives quick results with the major cost being size. A hi-level flow is found in the figure.

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Floating Point Adder for IEEE Floating Point Standard-754

      The disclosed adder takes advantage of anticipate circuits.
There is a parallel activity during the addition portion that takes
advantage of characteristics of IEEE Floating Point Standard - 754.
The resulting adder gives quick results with the major cost being
size.  A hi-level flow is found in the figure.

      There are several distinct features to this adder flow.  One is
that the smallest operand is forced down the B-Rail of the adder
logic.  This is particularly important during subtract operations.
Another feature is the leading zero anticipate (LZA).  This removes
the critical leading zero detect path that is used for post
normalization.  The final two features are the round anticipate and
the increment anticipate.  Together, these reduce the critical
round-up path.

The data follows the following path:

1.  Pre-alignment
    a.  In Registers (Regs) - the two operands initially enter the
        data path.
    b.  Pre-alignment preparation
        1)  The operands are split into their respective sign (S),
            exponent (E), and fraction (F) components.
        2)  The exponents are compared in E sub a -E sub b.  If the
            carry out is equal to one, then E sub a is the greater of
            the two.  The result of the subtract may also be chosen
            later as the pre-alignment shift amount.
        3)  Perform E sub b - E sub a in parallel with E sub a - E
            sub b This is a second choice for pre-alignment shift
            amount.
        4)  The fraction to be aligned is chosen.  If E  sub  a  >  E
            sub b , then F  sub b is sent to be aligned.  Otherwise,
            F  sub a is sent to be aligned.
        5)  The alignment shift amount is chosen.  If E  sub a > E
            sub b, then E  sub a- E sub b is chosen.  Otherwise, E
            sub b- E sub a is chosen.
        6)  The sign is chosen.  If E  sub a  >  E sub b, then S  sub
            a is chosen.  Otherwise, S  sub  b is chosen.
        7)  The exponent is chosen.  If E  sub a  >  E sub b, then E
            sub a is chosen.  Otherwise, E sub b is ch...