Browse Prior Art Database

Method for Storing and Updating Power on Self Test and Basic Input/Output Code

IP.com Disclosure Number: IPCOM000105871D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 106K

Publishing Venue

IBM

Related People

Huynh, DQ: AUTHOR [+3]

Abstract

Disclosed is a method for storing a portion of code necessary for the start-up and operation of a computer system, such as the operating instructions normally called BIOS (Basic Input/Output System) code and the POST (Power-on-Self-Test) instructions used to test various components when power is turned on the system, in a solid-state memory which is both readable and writable, and which retains data when the system is powered down. Examples of solid-state memory devices with these capabilities are FLASH* memory and various types of EEPROM (Electically Erasable Programmable Read-Only Memory) memory. The use of this method allows this code to be updated.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Storing and Updating Power on Self Test and Basic Input/Output Code

      Disclosed is a method for storing a portion of code necessary
for the start-up and operation of a computer system, such as the
operating instructions normally called BIOS (Basic Input/Output
System) code and the POST (Power-on-Self-Test) instructions used to
test various components when power is turned on the system, in a
solid-state memory which is both readable and writable, and which
retains data when the system is powered down.  Examples of
solid-state memory devices with these capabilities are FLASH* memory
and various types of EEPROM (Electically Erasable Programmable
Read-Only Memory) memory.  The use of this method allows this code to
be updated.

      As shown in the figure, a computer includes a processor 1 with
a data bus 2 and an address bus 3 extending to a ROM (Read-Only
Memory) memory 4 including BIOS and POST code to be executed.  Data
bus 2 also extends to a Flash memory 5.  While ROM memory 4 contains
a minimal amount of code, consisting of instructions which will never
need changing, the remaining BIOS and POST instructions are stored in
Flash memory 5, where they may be updated as required.

      BIOS and POST instructions are accessed by processor 1 within a
defined ROM memory address space.  For example, processor 1 may be an
Intel 80386SX processor, and the ROM memory address space may be
defined as address space 0E0000 through 0FFFFF and FE0000 through
FFFFFF.

      After power-on, flip-flop 10 is reset by the -SYSTEM_RESET
signal, providing an input to gate 11, so that ROM memory 4 is
enabled, being addressed whenever the -ROM_ADDRESS signal, derived by
decoding the memory address and applied as the other input to gate
11, indicates that the memory address is within the ROM memory
address space.  Processor 1 executes code from ROM memory 4,
verifying some of the hardware subsystems to ensure their integrity
before data is brought in from the floppy drive or the hardfile.  For
example, this code may test the system DR...