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Cache Coherency in Massively Parallel Systems

IP.com Disclosure Number: IPCOM000105876D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 114K

Publishing Venue

IBM

Related People

Ekanadham, K: AUTHOR [+2]

Abstract

The problem of maintaining cache coherency is a problem that is influenced by scale. A different approach will be undertaken in a system which is massively parallel and the premium is placed on reduction of traffic. There are two problems associated with cache coherency in a multiprocessing system. The first problem concerns the freedom to update lines that are held on a shared basis. This problem can be handled in a massively parallel system by sacrificing processor cycles to reduce memory traffic. The second problem is to assure that Example 3 is not violated. This can be handled by invalidating lines which have been updated in the memory and not in the cache. By doing this operation at a STORE COMMIT, memory traffic is minimized and cache coherency is preserved.

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Cache Coherency in Massively Parallel Systems

      The problem of maintaining cache coherency is a problem that is
influenced by scale.  A different approach will be undertaken in a
system which is massively parallel and the premium is placed on
reduction of traffic.  There are two problems associated with cache
coherency in a multiprocessing system.  The first problem concerns
the freedom to update lines that are held on a shared basis.  This
problem can be handled in a massively parallel system by sacrificing
processor cycles to reduce memory traffic.  The second problem is to
assure that Example 3 is not violated.  This can be handled by
invalidating lines which have been updated in the memory and not in
the cache.  By doing this operation at a STORE COMMIT, memory traffic
is minimized and cache coherency is preserved.

      In conventional multiprocessor designs the issues that relate
to the maintenance of cache coherency focus on the retaining
processor performance.  Thus in these systems, lines within
individual caches are held exclusive and in some cases the lines
which are brought into the cache, based on operand fetch, are brought
in exclusive.  The point of such an approach is to allow the
processor to store into lines without wasting cycles to first get the
line on an exclusive basis.  This type of activity on behalf of cache
coherency results in a concomitant increase in message and control
traffic.

      An attempt to maintain cache coherency in massively parallel
systems can involve the specification that certain data is cachable
and other data is not.  No coherency is guaranteed for cachable data,
and it becomes the programmers responsibility to determine which data
is cached and which data is not cached.  The decision to cache
impacts performance because if the data is in the memory, there is a
long latency time associated with accessing it.  The programmer is
usually not up to the task of making this cachable/non-cachable
decision and often takes a conservative approach by not-caching any
data.  This results in loss of performance.

      Within massively parallel systems the balance between processor
cycles that can be lost and traffic within the system to support
cache coherency switches over to the willingness to sacrifice
processor cycles to support a coherent memory hierarchy.  The
approach that is taken to this problem is to allow processors freer
access to all data and to determine a violation of the coherency of
the memory hierarchy at the point of the commit of a store update.
What is needed is clear-cut criteria that a store update can be made
or not made and a rollback of the committing processor to a suitable
checkpoint if its memory update is rejected due to a consistency
violation.

ALGORITHM THAT ASSURES CORRECT UPDATE OF MEMORY

o   Each line in the memory hierarchy has an entry of the global time
    when the last valid update was made to that line by any
    processor...