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High Density Thin Film Transistor Load SRAM Cell Using Trench DRAM Technology

IP.com Disclosure Number: IPCOM000105877D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 98K

Publishing Venue

IBM

Related People

Rajeevakumar, TV: AUTHOR

Abstract

The schematic vertical structure of the proposed SRAM cell is shown in Fig. 1. The cell uses a N+ substrate with N- epi. The substrate is biased at VDD, and the P-well is connected to the ground. LOCOS is used for device isolation. The p-mos Thin Film Transistor (TFT) load transistor is placed inside the trench. The TFT body poly is connected to the N+ substrate. A TiN barrier layer is used for the contact to prevent boron diffusing from the p+ poly layer to the n+ substrate. The gate poly for the bulk transistor also serves as the gate poly for the TFT. The multi-level strap connects the gate poly, TFT drain, and the n+ diffusion of the bulk transistor together. Metal level M1 is used for bitline wiring. Metal M2 is used for ground (VDD) contact and power supply (VDD) wiring. The substrate provides power to the cell.

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High Density Thin Film Transistor Load SRAM Cell Using Trench DRAM Technology

      The schematic vertical structure of the proposed SRAM cell is
shown in Fig. 1.  The cell uses a N+ substrate with N- epi.  The
substrate is biased at VDD, and the P-well is connected to the
ground.  LOCOS is used for device isolation.  The p-mos Thin Film
Transistor (TFT) load transistor is placed inside the trench.  The
TFT body poly is connected to the N+ substrate.  A TiN barrier layer
is used for the contact to prevent boron diffusing from the p+ poly
layer to the n+ substrate.  The gate poly for the bulk transistor
also serves as the gate poly for the TFT.  The multi-level strap
connects the gate poly, TFT drain, and the n+ diffusion of the bulk
transistor together.  Metal level M1 is used for bitline wiring.
Metal M2 is used for ground (VDD) contact and power supply (VDD)
wiring.  The substrate provides power to the cell.

      Fig. 2 shows the top view (layout) of the SRAM cell.  The
bitline wiring and the groundline wiring are not shown for clarity.
The cell is symmetric with split wordline layout.  The multi-level
strap used to contact two poly levels to diffusion is similar to the
surface strap of the trench DRAM.  The TFT transistor is placed
within the trench to reduce the cell area.  A simple method of
fabricating the cell structure, shown in Fig. 1, is outlined below.

      An n+ wafer with n- epi is used as the substrate.  First LOCOS
for device isolation is formed, followed by p-well implantation.  Pad
oxide and pad nitride is deposited, followed by the etching of 2 um
deep trench.  The trench depth should be larger than the epi
thickness.  A oxide collar is now formed around the trench.  The pad
nitride layer is now stripped, and a layer of TiSi sub 2/TiN is
deposited.  This deposited TiSi sub 2/TiN is etched off fro...