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Browse Prior Art Database

Random Access Memory Sharing through Clock Signal Interruption

IP.com Disclosure Number: IPCOM000105880D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 78K

Publishing Venue

IBM

Related People

Keener, DS: AUTHOR [+2]

Abstract

Disclosed is a circuit through which a single static Random Access Memory (RAM) memory module can be shared between two functions, such as an NVRAM (Non-Volatile Random Access Memory) system function and a SCSI subsystem function. To allow access to the memory module by the system function, the subsystem processor clock is turned off at a time when doing so does not interfere with subsystem operations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Random Access Memory Sharing through Clock Signal Interruption

      Disclosed is a circuit through which a single static Random
Access Memory (RAM) memory module can be shared between two
functions, such as an NVRAM (Non-Volatile Random Access Memory)
system function and a SCSI subsystem function.  To allow access to
the memory module by the system function, the subsystem processor
clock is turned off at a time when doing so does not interfere with
subsystem operations.

      As shown in the figure, a RAM module 1 is shared by a SCSI
subsystem interface 2 and a system interface 3.  Address multiplexer
4, data multiplexer 5, and write multiplexer 6 are used to determine
whether address, data, and write signals are transmitted to memory
module 1 from subsystem interface 2 or from system interface 3.
Control logic 7 provides an NVACCESS output signal which causes
multiplexers 4, 5, and 6 to switch to the inputs provided from system
interface 3.

      In the SCSI subsystem, instructions are contained in ROM (Read
Only Memory), not in RAM, so an access to ROM by the subsystem
processor is used to indicate that the subsystem processor is not
accessing RAM memory 1.  Thus, when system interface 3 requests an
access to NVRAM, as indicated by either the P9RDNV request to read or
the P9WRNV request to write signal provided as an input to control
logic 7, this logic does not respond directly to the system request,
but rather waits for the subsystem processor to acces...