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Sub-Quarter Micron MOSFETs with Inner Sidewall-defined Source/Drain Extensions

IP.com Disclosure Number: IPCOM000105893D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 100K

Publishing Venue

IBM

Related People

Acovic, A: AUTHOR [+3]

Abstract

Disclosed are several sub-quarter micron MOSFET (Metal Oxide Semiconductor Field Effect Transistor) structures realized by an extra doped poly layer for driving in ultra-shallow S/D (Source/Drain) junctions, and forming sidewalls to define sub-quarter micron gate length and various S/D extensions, e.g., (abrupt, LDD (Lightly Doped Drain) and FOLD (Fully Overlapped Lightly Doped drain). Sidewall-defined gate length eliminates the need for costly and/or time-consuming high-resolution lithography tools.

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Sub-Quarter Micron MOSFETs with Inner Sidewall-defined Source/Drain Extensions

      Disclosed are several sub-quarter micron MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) structures realized by an
extra doped poly layer for driving in ultra-shallow S/D
(Source/Drain) junctions, and forming sidewalls to define sub-quarter
micron gate length and various S/D extensions, e.g.,  (abrupt, LDD
(Lightly Doped Drain) and FOLD (Fully Overlapped Lightly Doped
drain).  Sidewall-defined gate length eliminates the need for costly
and/or time-consuming high-resolution lithography tools.

      Scaling down the channel length and the S/D junction depth are
the major challenges in improving MOSFET performance and density.
Because of the limited resolution of optical lithography, realizing a
sub-quarter micron gate length usually requires costly X-ray
lithography or time-consuming E-beam lithography.  Meanwhile, more
complicated processes such as including an extra pre-amorphorization
step become inevitable to form ultra-shallow S/D junctions needed for
sub-quarter micron devices.

      To reduce the cost raised by expensive lithography tools or by
process complexity in developing a sub-quarter micron MOSFET, we
disclose three MOSFET structures (Figs. 2, 3 and 4) which utilize
optical lithography plus sidewall techniques to define sub-quarter
micron gate lengths, and introduce an extra doped poly layer to form
ultra-shallow S/D junctions.  The devices disclosed achieve various
drain structures (abrupt, LDD and FOLD) for different applications by
slightly modifying the sidewall technology.  Since the gate poly can
overlap the S/D polys in the devices disclose...