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Browse Prior Art Database

Trench Capacitor or Stacked Capacitor with Increased Area

IP.com Disclosure Number: IPCOM000105900D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Hodgson, RT: AUTHOR [+3]

Abstract

Disclosed is a structure and a method of increasing surface area of stack and trench capacitors for semiconductor memories. Such capacitors can not be scaled as transistor devices since the charge needed to drive lines and devices does not scale down in the same way as the devices. As the ground rules shrink and the capacitor perimeter shrinks, the depth of the trench to width of the trench ratio increases.

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This is the abbreviated version, containing approximately 66% of the total text.

Trench Capacitor or Stacked Capacitor with Increased Area

      Disclosed is a structure and a method of increasing surface
area of stack and trench capacitors for semiconductor memories.  Such
capacitors can not be scaled as transistor devices since the charge
needed to drive lines and devices does not scale down in the same way
as the devices.  As the ground rules shrink and the capacitor
perimeter shrinks, the depth of the trench to width of the trench
ratio increases.

      We disclose that the techniques for making porous silicon can
be used to make pores in the silicon in the trench area which are
perpendicular to the surface and which have very large depth to width
ratios.  The surface area of a capacitor can thus be made very large
for a small surface area of silicon.

      An insulting film 1 (photoresist, oxide etc.) is applied over
the surface 2 of a semiconductor wafer 3 and holes 4 opened in the
film 1.  The wafer 3 is then immersed with the surface 2 in contact
with in an aqueous or ethanolic HF mixture 5 and a voltage is applied
between an electrolyte bath 6 in contact with the back side of wafer
3 and the mixture 5.  The anodic etching of the area 4 left
uninsulated on the wafer surface will result in a neetwork of pores 7
perpendicular to the wafer surface 2 reaching to a depth 8 determined
by the etching time and HF mixture characteristics.  Pores can, in
fact, be etched right through the wafer!  The diameter 9 of the pores
7 can be co...