Browse Prior Art Database

Technique to Minimize Delays Caused by Memory Store Page Defaults

IP.com Disclosure Number: IPCOM000105902D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 108K

Publishing Venue

IBM

Related People

Bowen, NS: AUTHOR

Abstract

A page fault in a virtual memory system is costly in terms of instructions to resolve the fault, cache disruption due to context switches and time delays to fetch the page. This invention proposes a technique to avoid having to delay for some page faults caused by memory stores.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Technique to Minimize Delays Caused by Memory Store Page Defaults

      A page fault in a virtual memory system is costly in terms of
instructions to resolve the fault, cache disruption due to context
switches and time delays to fetch the page.  This invention proposes
a technique to avoid having to delay for some page faults caused by
memory stores.

      This invention describes a technique to allow a process to
continue forward execution in spite of a page fault caused by a store
operation.  When the page fault occurs for a program store, instead
of suspending the process while the page is fetched from the paging
device, a description of the store action (e.g., offset in page and
new data value) is traced in a special buffer referred to as a
write-fault buffer (WFB).  The WFB is associated with the virtual
page so that subsequent stores to the page use the same WFB.  The
program is allowed to continue execution while the page fault is
asynchronously resolved.  When the page fault is resolved, the stores
traced in the WFB are applied to the memory page and the page is then
mapped into the virtual memory.  Any attempts to read from the page
(e.g., data fetch, instruction fetch) must result in a suspension
(unless the data is contained in the WFB).  Upon a page fault, the
paging operation would be asynchronously started and a special
write-fault buffer would be allocated.  The page table would indicate
that the paging operation is in progress and the location of the WFB
would be provided.  The WFB would contain information consisting of
the address of the current free entry in the WFB and possibly (if not
an architected feature) the maximum number of entries allowed in the
WFB.  For each subsequent store-page fault, the prior buffer entries
do not have to be checked for duplicate store locations.   If there
are multiple stores to the same location, the data will be correct as
long as the WFB buffer is applied to the page in the forward order.
Thus, each subsequent fault is processed by saving the data value and
the offset of the store in the WFB and incrementing the current free
pointer into the WFB.

      The bit I in the virtual page table is the traditional
"invalid" bit which indicates whether the page is mapped into real
storage.  If this bit is 0 then the page table contains the real
storage address for the virtual page.  This invention requires the
addition of a new bit, W, which is used to indicate the status of the
WFB.  We shall use the notation (I,W) for these two bits (the meaning
of these bits are summarized in -- Fig 'WFB2' unknown --).  When the
page is not allocated in real storage these two bits are (1,0).  When
a store fault occurs, a WFB is allocated and its address is copied
into the page table (in the same location that would normally contain
the real frame address).   The bits are set to (1,1) which means that
the page is still invalid but a WFB has been allocated.  The
following figure...