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Method Avoiding a Power-Up Surge Current

IP.com Disclosure Number: IPCOM000105905D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR

Abstract

Disclosed is a method which avoids a potential surge current in sense amplifier latches which may overload the power supplies.

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Method Avoiding a Power-Up Surge Current

      Disclosed is a method which avoids a potential surge current in
sense amplifier latches which may overload the power supplies.

      The sense lines SAT and SAC of the differential sense amplifier
drive the sense amplifier latch.  With the help of the p-FET T15 (as
shown in the Figure) between the sense lines SAT and SAC of the
differential sense amplifier a VDD - GND path is avoided during a
power-on sequence.  The additional FET pulls the node SAC up if SAT
and SAC are at first down.  Thus, the state SAC and SAT both down is
eliminated.