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Hierarchical and Reconfigurable Test Control Structure Useable for System Diagnostic Functions

IP.com Disclosure Number: IPCOM000105928D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 130K

Publishing Venue

IBM

Related People

Berry Jr, RW: AUTHOR [+7]

Abstract

Disclosed is a test control bus structure with a three level hierarchy of control which is useable for chip and multichip module (MCM) test and which allows usage of hardware included for test functions for system alter/display/reset/scan functions. The control of test functions designed into each chip uses a common test control bus which is used to control chip test functions when the chip is in a chip tester, module test functions when the chips are mounted on the MCM and the MCM is in a module tester and system self-test functions and system alter/display/reset/scan functions when the module is plugged into the system. This control bus structure forms a three level logical control hierarchy composed of chip tester, MCM tester and System Logic Support Station (LSS)/Processor controller.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Hierarchical and Reconfigurable Test Control Structure Useable for System Diagnostic Functions

      Disclosed is a test control bus structure with a three level
hierarchy of control which is useable for chip and multichip module
(MCM) test and which allows usage of hardware included for test
functions for system alter/display/reset/scan functions.  The control
of test functions designed into each chip uses a common test control
bus which is used to control chip test functions when the chip is in
a chip tester, module test functions when the chips are mounted on
the MCM and the MCM is in a module tester and system self-test
functions and system alter/display/reset/scan functions when the
module is plugged into the system.  This control bus structure forms
a three level logical control hierarchy composed of chip tester, MCM
tester and System Logic Support Station (LSS)/Processor controller.
This hierarchy allows the control at the lower level to have highest
priority, so that the LSS has control of the test bus only when the
MCM is plugged in the system.

      Three types of chips are typically used in a bipolar VLSI high
performance system based on masterslice designs: pure logic chips
without arrays, chips with integrated arrays and chips with embedded
arrays.  Integrated arrays are physical custom RAM macros with custom
designed support logic and unique clocking placed on a unique
masterslice.  Standard logic masterslice cells may also be placed on
chips with integrated arrays in the area not occupied by the RAM
functions.  Embedded arrays are logical RAM macros made up of
standard logic masterslice cells.  Each chip type has unique test
hardware, for example the SCAT hardware of [*]  used on integrated
arrays.  The sequences and logical connections required to accomplish
the system and test functions differ for each chip type.  Any test
bus structure must accomodate all types of chips intermixed on the
same second level package.

The hierarchical test bus structure disclosed here is implemented
primarily by the following two logical functions:

1.  Every chip of each of the above three types implements a common
    test control structure composed of a 5 bit test bus with decodes
    of the values on this bus enabling various test functions.  The
    truth table of these decodes is common accross all chip types,
    with each chip implementing that subset of the decodes needed to
    control test function on that chip.

2.  Logic associated with the test bus at the MCM level recognizes
    the condition when the external module level package tester is
    controlling the bus and relinquishes control to the tester.  When
    the tester is not in control, this logic (on the LSS and clock
    chips) allows LSS/ Processor Controller control of the bus.

      Chips of each type are put together on...