Browse Prior Art Database

Cache Tag RAM Diagnostic Mode

IP.com Disclosure Number: IPCOM000105965D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Ferrarini, S: AUTHOR [+6]

Abstract

Disclosed is a cache controller function which places cache memory into a special "diagnostic tag test mode" in which cache memory can be written directly. The tag RAM's, are also updated, as they would be in a standard linefill situation to the cache memory. In normal operation, the tag RAM's provide an indication when a current address on the bus "hits" a line stored in cache memory. Any additional accesses to a cache line, to which original data has been written, results in a cache hit, forcing a read or write to the cache.

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This is the abbreviated version, containing approximately 65% of the total text.

Cache Tag RAM Diagnostic Mode

      Disclosed is a cache controller function which places cache
memory into a special "diagnostic tag test mode" in which cache
memory can be written directly.  The tag RAM's, are also updated, as
they would be in a standard linefill situation to the cache memory.
In normal operation, the tag RAM's provide an indication when a
current address on the bus "hits" a line stored in cache memory.  Any
additional accesses to a cache line, to which original data has been
written, results in a cache hit, forcing a read or write to the
cache.

      On the other hand, a standard cache memory is loaded only by
transferring a cache line from another memory, such as system memory,
into the cache memory.  Thus, a standard cache memory cannot be
tested before another memory is actually in use.

      After leaving the new "diagnostic tag test mode," cache memory
behaves according to a standard cache algorithm.  The new mode is
disabled, so that an optimal algorithm is provided for software
applications.

      The new mode is defined as working over a predetermined address
range, which can be used as cache memory.  The boundary of this
address range is used to ensure that code executing the test is not
cacheable.  This mode can be used following another test procedure,
in which it is determined that the SRAM's are good entities and that
a lower address portion of system memory is good.

      Test procedures include first writing t...