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Browse Prior Art Database

Corner/Edge Functional Monitors of Large Area Interconnects

IP.com Disclosure Number: IPCOM000106008D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 92K

Publishing Venue

IBM

Related People

Deutsch, A: AUTHOR

Abstract

Disclosed is a corner/edge functional monitor for large-area-chip-to-chip interconnects such as used in [1], with a X- and Y-directed transmission lines between two references.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Corner/Edge Functional Monitors of Large Area Interconnects

      Disclosed is a corner/edge functional monitor for
large-area-chip-to-chip interconnects such as used in [1], with a X-
and Y-directed transmission lines between two references.

      It is proposed to place probing pads at the four corner edges
of the multi-chip carrier, outside of the active area.  These test
points connect to two pairs of transmission lines that traverse, as
much as possible, and in all directions, the entire area of the
substrate, with a possible configuration as shown in the Figure.  The
four wiring channels have to be reserved for these monitors but this
represents a very small penalty, of the order of 0.05%  of the total
number of wiring tracks available on a typical substrate.  The long
transmission lines travel by switching between X- and Y-directed
paths through interconnecting vias.  At the four corners, on the edge
of the chip sites, the coaxial probing pads can have a configuration
as shown in the inset the Figure, with signal and reference pads in
close proximity, to accommodate launching and detecting of high-speed
signals with risetimes and amplitudes representative of the driver
circuit characteristics found on the logic chips.  The ends of the
long lines and the reference planes extend outside of the chip site
for about 200 &mu.m in order to preserve the controlled transmission
line environment throughout.

      Measurements of the line resistance can verify the
metallization fabrication integrity as well as the uniformity and
dimensional accuracy of the cross section.  Since the lines travel
through both X and Y layers and then connect to top surface test
pads, any inter-layer via contact resistance problem within the
critical active area can be identified.  Self and mutual capacitance
measurements verify the integrity of the insulation dielectric
constant of the entire transmission line structure especially if
composite materials are used in the stack.  Topology variations of
lines width or thickness variations can be identified in this
measurement as well.

      Launching of high speed signals at one end of these lines and
detecting them a t the other end with coaxial probes provides a
wealth of information regarding the functional characteristics of the
chip-to-chip wiring.  The propagation delay, &tau., is directly
dependent on the line inducta...