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Collision Vector Table Logical Address, Physical Address, Flag and Valid Bit Fields Description, Function and Use

IP.com Disclosure Number: IPCOM000106041D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 76K

Publishing Venue

IBM

Related People

Karim, F: AUTHOR [+4]

Abstract

CVT entries consists of LA, PA, Flag and Valid bits. LA stands for Logical address, and is the architected address of the registers. PA stands for physical address and as the name implies, is the physical register implemented. CVT stands for Collision Vector Table and has the following tasks: Integrity of sequentiality, Register recycling, Collision prevention, Assisting in Interrupts, and prevention of WAW and WAR hazards.

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Collision Vector Table Logical Address, Physical Address, Flag and Valid Bit Fields Description, Function and Use

      CVT entries consists of LA, PA, Flag and Valid bits.  LA stands
for Logical address,  and is the architected address of the
registers.  PA stands for physical address and as the name implies,
is the physical register implemented.  CVT stands for Collision
Vector Table and has the following tasks:  Integrity of
sequentiality,  Register recycling, Collision prevention,  Assisting
in Interrupts, and prevention of WAW and WAR hazards.

      There is one table per Register File.  For example one for
FPRs, one for GPRs,  and one for CCRs.  The tables have 24 entries
arranged in 6 groups of 4.  The CVT pointer points to a group of 4 at
any given time.  A high level CVT structure is depicted in the
figure.

      LA and PA are implemented using 6 bits each.  The flag field is
1 bit wide.  There is a floating point, a fixed point, a CCR, and a
Ld/St flag.  These flags get set to indicate what kind of instruction
is using that CVT entry,  so for a FP type instruction, the floating
point flag will be set.  The valid bits field is 2 bits wide.  The
truth table for the Valid field is shown below:

             Vld0   Vld1   |       Meaning
           ----------------|-----------------------
              0      0     |       Invalid
              0      1     |   Non Speculative
              1      0     |   Speculative Seq.
              1      1     |  Speculative Target

The Valid field is a major player during speculative execution due to
branches.

      Instructions are generally of the type   OPC   RT,RA,RB.
Where, OPC is the opcode,  RT, RA and RB are the target and source
registers respectively.  The architecture makes use of 32 Floating
point, and 32 fixed point, registers.  However,  the number of
physical registers implemented is 64 for each.  The source and target
registers of the instruction stream get renamed to physical registers
and get di...