Browse Prior Art Database

Technique for Executing CISC Instructions in Multiples and Out-of-Order

IP.com Disclosure Number: IPCOM000106075D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 6 page(s) / 188K

Publishing Venue

IBM

Related People

Dwyer III, H: AUTHOR

Abstract

Disclosed is an instruction processing technique that improves performance over that of conventional processors by executing CISC instructions in multiples and out-of-order when possible.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 40% of the total text.

Technique for Executing CISC Instructions in Multiples and Out-of-Order

      Disclosed is an instruction processing technique that improves
performance over that of conventional processors by executing CISC
instructions in multiples and out-of-order when possible.

      A block diagram of a processor implementing the technique is
shown in Fig. 1.  The Issue Unit (IU) fetches multiple instructions,
partially decodes them and schedules them for execution.  The IU may
issue selected instructions in multiples and out-of-order when
possible to available functional units (FUs) each cycle.  A FU
executes an instruction under the guidance of the IU, accessing
memory and the register file as necessary.  The functional unit
signals an instruction's completion by returning its tag to the IU.
The IU periodically eliminates completed instructions from the
processor and fetches new instructions into it.

      The IU detects an instruction's register dependencies and
issues the instruction and a unique tag to a FU when it is possible
to initiate the instruction's execution.  The IU schedules the
actions to be performed by the FU by re-issuing the instruction's tag
at appropriate times.  This signals the FU that it may enter the next
phase of an instruction's execution.  An example is presented below.

      A block diagram of the Issue Unit is shown in Fig. 2.  It
consists of an array of slots (the stack) each of which may contain
an instruction.  Instructions are brought into the IU and inserted
into slots based on their order of precedence with the instruction of
highest precedence in slot 0.  As instructions complete execution
they are removed from the stack, remaining ones are compressed
upwards into empty slots, and new instructions are fetched into the
IU.  Thus, instructions in the stack maintain their instruction
stream order while they may be issued and executed out-of-order.

      Because this order is maintained, the detection of register
usage conflicts between instructions is simplified.  Logic in each
slot compares the register usages of the instruction that it contains
with the register usages of instructions in the slots above it, i.e.,
with those of instructions of high precedence.

      When an instruction enters the IU, its register usages are
represented in arrays of bits:  one array for the register it reads
(a read-vector) and one array for the registers that it writes (a
write-vector).  Fig. 3 shows an example instruction with its read and
write vectors and tag.  The tag is an array of bits with length equal
to the number of instructions that may be concurrently in the
processor.  Only one, unique, bit position is set to one in each tag.
A CU or tag of length eight is shown.  Tags have this structure so
that any combination of tags may be asserted on the tag bus
concurrently.  This capability is necessary because any combination
of instructions may compete during a given cycle.  The FUs...