Browse Prior Art Database

High-Performance Array Chip with Half-Cycle Interleave

IP.com Disclosure Number: IPCOM000106080D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 127K

Publishing Venue

IBM

Related People

Engel, OP: AUTHOR [+5]

Abstract

The high-performance array chip with half-cycle interleave is a single chip hybrid memory system incorporating interleaving and pipelining memory access techniques to provide an extremely high-performance memory system suitable for a single chip. This memory system provides two reads and two writes within one and one-half cycles of the memory array. The access ports include: one read address bus, one write address bus, one input data bus, one output data bus, and five cycle control signals.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

High-Performance Array Chip with Half-Cycle Interleave

      The high-performance array chip with half-cycle interleave is a
single chip hybrid memory system incorporating interleaving and
pipelining memory access techniques to provide an extremely
high-performance memory system suitable for a single chip.  This
memory system provides two reads and two writes within one and
one-half cycles of the memory array.  The access ports include: one
read address bus, one write address bus, one input data bus, one
output data bus, and five cycle control signals.

      Although the preferred embodiment employs this single-chip
memory system for vector-processing registers, the description will
make a wide variety of additional uses become intuitively obvious to
one skilled in the art.

      The present design relates to a memory system that incorporates
both interleaving and pipelining techniques to provide an extremely
high-performance hybrid memory system suitable for a single chip.

      In recent years, pipelining techniques have displaced
interleaving techniques to provide higher performance for memory
access and to gain greater component utilization efficiency.
Although this technique indeed provides higher performance than the
interleaving technique, the performance is still limited by the array
access cycle.

      The present design employs both interleaving and pipelining
techniques to overcome the array access cycle limitation.  It
provides a chip-contained memory system with a high-performance
hybrid access mechanism for a 256x72-bit static random access memory.
The chip can be personalized for operation in one of two modes: full
cycle concurrent, 256x72-bit or half-cycle interleaved 2x128x72-bit.

      As shown in Fig. 1, the memory system suitable for a
single-chip design comprises two memory arrays 104 and 105 which can
be operated concurrently or out of phase to provide an interleave
access and means for receiving and registering alteration data 101,
102 and 103, means for sensing synchronized sets of data selected
from the arrays and registering for driving 106 and 107 read access
bus 108, and means for addressing and control logic 109-140,
subsequently described.

      To establish the operation as concurrent or interleave access,
a means not illustrated to latch the state is set up during
initialization.  Additionally, the two externally connected clock
signals 119 and 120 must be concurrent when operating with concurrent
access and 180 degrees out of phase when operating...