Browse Prior Art Database

Hardware String Search Mechanism

IP.com Disclosure Number: IPCOM000106087D
Original Publication Date: 1993-Sep-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Barcelo Jr, P: AUTHOR [+3]

Abstract

Disclosed is a method and mechanism for executing independent string searches in parallel with other processor activities, thereby achieving a form of parallel processing at the memory bank level.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 49% of the total text.

Hardware String Search Mechanism

      Disclosed is a method and mechanism for executing independent
string searches in parallel with other processor activities, thereby
achieving a form of parallel processing at the memory bank level.

      As shown in Fig. 1, to implement this method, a hardware string
search mechanism (HSSM) 10 is connected to a local bus 11 extending
from a system processor 12, to an I/O bus 13, and to a system bus 14
extending to a memory controller 15 associated with memory 16.  Cache
memory 17 may optionally also be connected to local bus 11, with a
CACHE ENABLE signal being provided by HSSM 10.

HSSM 10 consists of circuits including the following registers:

     (A)  Target String Start Address Register
     (B)  Target String End Address Register
     (C)  Search Range Start Address Register
     (D)  Search Range End Address Register
     (E)  Search Status Block Pointer Register
     (F)  Occurrence Found Register
     (G)  Target String Character Pointer Register
     (H)  Search Range Character Pointer Register
     (I)  Temporary Register
     (J)  Control Register

      Specific search requirements are set in Control Register (J) by
the processor 12.  This register is an eight-bit register, providing
options for processor 12 in accordance with the following bit
definitions:

     Bit 0.  START = start of search
     Bit 1.  F/A = first/all
     Bit 2.  IE = interrupt enable
     Bit 3.  SD = search direction

When Bit 0 is set to a value of one, a string search is begun.  If
Bit 1 is set at a one level, the search is terminated as successful
when the first matching character is found; otherwise the search is
continued until a match is found between all characters.  When Bit 2
is set at a one level, an interrupt function is enabled.  When Bit 3
is set at a zero level, the search pointers are incremented during
the search operation; otherwise, they are decremented.

      When processor 12 requires a string search, the processor
programs registers (A) through (E), listed above, and sets the
specific search requirements in control register (J).

      As shown in Fig. 2, HSSM 10 functions as a state machine, with
state 21 checking Bit 0 of control register (J) to determine if a
search is to be executed.  If this bit indicates the START condition,
the state machine proceeds to an initialization state 22, in which
Search Range Character Pointer Register (H) is initialized from
Search Range Start Address Register (C) and Search Range End Address
Register (D).  Next, in reset state 23, Target String Character
Pointer Register (D) is initial ized from Target String Start Address
Register (A).  Then, in first arbitration state 24, bus control is
arbitrated from processor 12.  When this arbitration is successful,
in state 25, the memory contents identified in Target String
Character Pointer Register (D) is copied into Temp...