Browse Prior Art Database

Magnetic Media Bus

IP.com Disclosure Number: IPCOM000106139D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 130K

Publishing Venue

IBM

Related People

Cleveland, LD: AUTHOR [+4]

Abstract

The Magnetic Media Bus is a synchronous internal bus architecture for a multiple chip I/O Processor. This design provides a high speed, low latency, low I.O count, Burst DMA interface. It separates the DMA channel from the controlling processor's instruction fetch data bus, thus providing very high speed data movement without impacting the IOPs processor performance. It also provides guarantied data rates and latency to devices. The design is simple to implement, does not have complex timing requirements, and provides a powerful DMA control function. It is also flexible, in that it will allow 1-4 slave chips to attach.

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Magnetic Media Bus

      The Magnetic Media Bus is a synchronous internal bus
architecture for a multiple chip I/O Processor.  This design provides
a high speed, low latency, low I.O count, Burst DMA interface.  It
separates the DMA channel from the controlling processor's
instruction fetch data bus, thus providing very high speed data
movement without impacting the IOPs processor performance.  It also
provides guarantied data rates and latency to devices.  The design is
simple to implement, does not have complex timing requirements, and
provides a powerful DMA control function.  It is also flexible, in
that it will allow 1-4 slave chips to attach.

The Magnetic Media Bus consists of the following nets.

Status Select     4 lines total, 1 line per slave, minus active,
                  driven by Slave.  Driven active for a status cycle,
                  status is passed from the slave to the master.
                  Driven inactive when DMA data is passed between the
                  slave and master.  The slave must drive this active
                  or inactive at least one clock time before it
                  drives DMA Request, and it must hold that level for
                  at least one clock time after it negates DMA
                  Request.

DMA Request       4 lines total, 1 line per slave, minus active,
                  driven by Slave.  Driven active when the slave is
                  requesting either a status cycle or a DMA cycle.
                  The slave can drive this line at any time.  For a
                  Status cycle, it must be negated one clock time
                  before the end of the DMA Acknowledge.  For a DMA
                  request, it should be negated one clock time before
                  the end of the DMA Acknowledge.  If it is negated
                  at any other time, then the master may or may not
                  drive another DMA Acknowledge on the cycle
                  following DMA Request being negated.

DMA Ack           1 line, minus active, driven by Master.  Driven
                  active for a cycle (2 clock times) for each slave
                  requests.  Can be driven either back to back or
                  with any number of idle clocks between cycles.

Data              16 data lines, 2 parity lines.  Parity is odd.
                  Minus active, driven by the Master on write DMAs,
                  driven by the Slave on read DMAs and Status Cycles.

                        The master will TRI-STATE these lines...