Browse Prior Art Database

Design of a Totally Interlocked Data Path for Noise Reduction

IP.com Disclosure Number: IPCOM000106144D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Barth, JE: AUTHOR [+4]

Abstract

An interlocked data path is described in which off chip driver (OCD) outputs are forced to their high-impedance or tri-state mode during intervals when the OCD input data source is switching from one data source address to another. When address transitions are detected, an Address Transition Detected (ATD) pulse propagates through a delay path that is identical to that of the data path to the OCDs. The ATD pulse triggers OCD Control Logic that enables the tri-state mode at precisely the correct time to prevent spurious OCD output transients during the address transition interval.

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Design of a Totally Interlocked Data Path for Noise Reduction

      An interlocked data path is described in which off chip driver
(OCD) outputs are forced to their high-impedance or tri-state mode
during intervals when the OCD input data source is switching from one
data source address to another.  When address transitions are
detected, an Address Transition Detected (ATD) pulse propagates
through a delay path that is identical to that of the data path to
the OCDs.  The ATD pulse triggers OCD Control Logic that enables the
tri-state mode at precisely the correct time to prevent spurious OCD
output transients during the address transition interval.

      A block diagram of one implementation of the interlocked scheme
is shown in the figure.  The ADDRESS TRANSITION DETECT block
generates an ATD pulse whenever any address changes state, and passes
the ATD pulse and the address code to the BIT DECODE block.  The BIT
DECODE block selects one of many bit switches and enables the
SECONDARY SENSE AMPLIFIER in response to new bit addresses.  As the
addresses change state, the ATD pulse deselects all bit switches and
SECONDARY SENSE AMPLIFIERS.

      The SECONDARY SENSE AMPLIFIER amplifies the data from the
selected array data bitlines and transmits the data to the OCD via
the DATA LINE.  The ATD pulse propagates along the DUMMY DATA LINE
which duplicates precisely the delay of the DATA LINE so that the OCD
CONTROL LOGIC will enable the OCD tri-state mode only du...