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Planar Memory Boundary Registers with Reclaim Feature

IP.com Disclosure Number: IPCOM000106145D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 190K

Publishing Venue

IBM

Related People

Stelzer, KC: AUTHOR

Abstract

Disclosed is a feature providing a way to use address locations of planar (system board) memory, in a reclaim address range beyond the physical range of the active memory banks of the system. To use this feature, a reclaim function must be active for one of the memory banks of the system. When an attempt is made to access the reclaim address range, a corresponding address, within the memory bank for which the reclaim function is active, is accessed. The corresponding address is determined by adding an index number to the address, within the reclaim range, for which the access attempt is made. The index number is generated by adding one to the ending address of the bank which has been programmed to have reclaim enabled, and by subtracting the starting address of the reclaim range from the result.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 36% of the total text.

Planar Memory Boundary Registers with Reclaim Feature

      Disclosed is a feature providing a way to use address locations
of planar (system board) memory, in a reclaim address range beyond
the physical range of the active memory banks of the system.  To use
this feature, a reclaim function must be active for one of the memory
banks of the system.  When an attempt is made to access the reclaim
address range, a corresponding address, within the memory bank for
which the reclaim function is active, is accessed.  The corresponding
address is determined by adding an index number to the address,
within the reclaim range, for which the access attempt is made.  The
index number is generated by adding one to the ending address of the
bank which has been programmed to have reclaim enabled, and by
subtracting the starting address of the reclaim range from the
result.

      This method provides the ability to reclaim planar (system
board) memory locations for use, when these locations are in an
address range used by one or more memory mapped Busmasters.  An
address range outside the ranges assigned to the various memory banks
is chosen to be the reclaim address range.  When an attempt is made
to access this reclaim address range, the address is changed to an
address in the range used by a memory mapped Busmaster.

      The use of address ranges and the index number may be
understood in reference to the following example, in which memory
addresses are expressed as decimals representing binary numbers
corresponding to certain ordered bits in the memory addresses.  The
level of significance of these bits is determined by the fact that
each memory bank, in this example, has 15 Megabytes of memory.  In
this example, a system has three active memory banks, with Bank 0
having an address range from 0 to 9, Bank 1 having an address range
from 16 to 31, and Bank 2 having an address range from 32 to 39.  The
address range of 10 to 15 in Bank 0 is allocated to memory mapped
Busmasters.  The reclaim address range is 40 to 45, just above the
range of active memory.  Thus, if Bank 0 is programmed to have
reclaim enabled, the index number, generated by adding 1 to 9 and by
subtracting 40 from the result, is equal to -30.  When this number is
added to an address in the reclaim range, from 40 to 45, the result
is a number in the range of Bank 0 allocated to memory mapped
Busmasters, from 10 to 15.

      Fig. 1 provides a block diagram of the Bank 0 address decode.
A starting address register 1 holds the starting address for each
bank of planar memory, while ending address register 2 holds the
ending address range for each bank of planar memory.  Starting
reclaim address register 3 and ending reclaim address register 4
holds the starting and ending addresses, respectively, of the reclaim
address range.  As in the previous example, addresses in registers 1
through 4 are stored as binary bit values with certain ordered levels
of significan...