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High Performance CMOS Off-Chip Driver Circuit with Minimal Switching Noise

IP.com Disclosure Number: IPCOM000106169D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 137K

Publishing Venue

IBM

Related People

Herrman, BD: AUTHOR [+2]

Abstract

Described is a high performance CMOS off-chip driver (OCD) circuit that reduces switching noise without altering high speed operation. The circuit profices a current diverting technique based on a device ratio design which dissipates DC power in a variable OCD switching circuit.

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This is the abbreviated version, containing approximately 51% of the total text.

High Performance CMOS Off-Chip Driver Circuit with Minimal Switching Noise

      Described is a high performance CMOS off-chip driver (OCD)
circuit that reduces switching noise without altering high speed
operation.  The circuit profices a current diverting technique based
on a device ratio design which dissipates DC power in a variable OCD
switching circuit.

      In variable OCD switching circuitry, the switching speeds over
the operational temperature range and the adverse Ldi/dt noise due to
simultaneous switching of OCDs at low temperature can be detrimental
to the optimal performance of the circuits involved.  The concept
described herein provides a means of minimizing the Ldi/dt and the
temperature effects on driver propagation delay and di/dt noise by
providing relief for the excessive power consumption by pulsing the
current diverting devices.

      The concept uses a current diverting device that is logically
controlled.  Its ON time can be varied to meet a variety of design
conditions.  For example, an inverter can be changed to a NOR or a
NAND allowing for an enable or a disable input to be added to the
design.  This provides additional levels of flexibility.  In
addition, a multiple number of delay paths can be implemented in
parallel as long as each path has a unique enable/disable input.
This allows for an overall programmable or selectable delay.

      The delay function of the concept is constructed from CMOS
logic gates that can be integrated into existing OCD designs with
minimum area and performance impact.  The concept demonstrates a
means of providing relief for excessive power consumption by reducing
the duty cycle of the current diverting device.  The amount of time
that the DC current is passing through the current diverting devices
will match the OCDs faster transition times.

      The current diverting technique provides a digitally controlled
current diverting device which is always OFF so as to minimize DC
power dissipation.  The device is only activated when the OCD is in
transition to AC power.  The current diverting circuit is used to
temperature compensate the OCD with minimal DC power dissipation.  By
lowering the effective Ldi/dt noise, the design enables more OCDs to
be switched.

      A bit steering concept is used to temperature compensate an OCD
is selectively pulsed ON coincident with the OCDs falling output
transitions rather than prior act circuitry that required the current
steering device to be continuously conducting.  The CMOS OCD circuit
topology is shown in the figure.

      The P- field effect transistor (FET) pullup output stage device
P17 is controlled by CMOS AND gate circuitry P5, P6, P7, REXA, N8, N9
and N10.  The N-FET pull down N18 is gated by CMOS NOR circuitry P13,
P12, P11, REXB, N14, N15 and N16.  REXA and REXB are current limiting
resistors.  RUP and RDN are output series resistors used to match the
transmission lines (not shown). ...