Browse Prior Art Database

Non-Disruptive Clock Switching Mechanism

IP.com Disclosure Number: IPCOM000106173D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 128K

Publishing Venue

IBM

Related People

Feraud, J: AUTHOR

Abstract

Disclosed is a circuit that allows to DYNAMICALLY switch the clocking applied to a logic system or sub-system (Processor, Storage Controller, etc...) when some modes of operation like initialization or maintenance cannot be run at the real functional speed " this case may happen for instance when a maintenance processor or any device used in the initialization or maintenance operations only works at lower speeds than the functional processor.

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This is the abbreviated version, containing approximately 52% of the total text.

Non-Disruptive Clock Switching Mechanism

      Disclosed is a circuit that allows to DYNAMICALLY switch the
clocking applied to a logic system or sub-system (Processor, Storage
Controller, etc...) when some modes of operation like initialization
or maintenance cannot be run at the real functional speed " this case
may happen for instance when a maintenance processor or any device
used in the initialization or maintenance operations only works at
lower speeds than the functional processor.

      The clock switching is totally non-disruptive in the sense that
the logic state of the system is absolutely not affected: indeed the
logic operation can be restarted in the "functional" timing at the
very point it had been stopped after a maintenance operation like a
read of system internal registers has been performed using the
"maintenance" timing.

      The proposed circuit takes advantage of the scan latches design
(named LSSD for Level Sensitive Scan Design within IBM) which is
widely used by many companies due to the high benefits it provides in
the test area:  each latch in the logic is split into a L1 latch
controlled by an A/C clock and this L1 latch feeds a L2 latch
controlled by a B clock.  The logic basically relies on the scan
design rule which states that an A/C clock can be gated by an L2
latch output and a B clock can be gated by a L1 latch output.

      The Fig. 2 circuit implementation is described in Fig. 1 and a
timing diagram is shown in ; on these figures, it is assumed that
timing 1 is the functional timing and that timing 2 is the init or
maintenance timing.

      Note that the SCAN TEST CLOCK (A input of latches) and the SCAN
TEST DATA inputs (I inputs of the latches) have not been wired in
Fig. 1 for better clarity (it does not add anything to the logic
understanding).  Only FUNCTIONAL clocks (C input of L1 latches and B
input of L2 latches) and functional datas (D input of F1 latches)
have been wired.

      The INIT or MAINTENANCE MODE input is always set active
(Logical level '1') from timing 1 and reset to inactive status
(Logical level '0') from timing 2.

      latches 1 and 2 allows to resynchronize the init or maintenance
mode signa...