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Optimized Patterns for Logic Product Burn-in

IP.com Disclosure Number: IPCOM000106179D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Schafer, JL: AUTHOR [+3]

Abstract

Disclosed is a method for generating optimized patterns to exercise the internal logic circuits for burn-in. Sequence of pattern pairs are chosen from the test patterns that generate most complementary internal states. The resulting patterns, a very small subset of the test patterns, produce nearly uniform switching at all internal logic gates during burn-in.

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Optimized Patterns for Logic Product Burn-in

      Disclosed is a method for generating optimized patterns to
exercise the internal logic circuits for burn-in.  Sequence of
pattern pairs are chosen from the test patterns that generate most
complementary internal states.  The resulting patterns, a very small
subset of the test patterns, produce nearly uniform switching at all
internal logic gates during burn-in.

The procedure to generate these patterns are as follows:

1.  Obtain the test patterns for stuck fault detection.

2.  For each pattern generate states for all internal gates.

3.  Define the first two burn-in patterns as the pattern pair that
    generate most complementary internal states.

4.  Delete all internal states that switching can be accomplished by
    the first two burn-in patterns.  The number of internal states is
    now reduced.

5.  Find the next burn-in pattern pair using the procedure outlined
    in step 3.

6.    Repeat 4 and 5 until all gates are exercised.

7.  Optimize the duty cycle of each burn-in patterns so that the
    deviation from 50% switching is minimized for each gate.