Browse Prior Art Database

Two Ported Memory Controller for High Speed CPUs

IP.com Disclosure Number: IPCOM000106184D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hardell Jr, WR: AUTHOR [+3]

Abstract

Disclosed is a means to have a high speed synchronous CPU port into memory while having the benefits of a fixed clock rate I/O-DMA interface into memory. Generic adapters would be put on the fixed clock bus (that is asynchronous with memory). CPUs or very high speed adapters would be put on bus that is synchronous with the memory.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 88% of the total text.

Two Ported Memory Controller for High Speed CPUs

      Disclosed is a means to have a high speed synchronous CPU port
into memory while having the benefits of a fixed clock rate I/O-DMA
interface into memory.  Generic adapters would be put on the fixed
clock bus (that is asynchronous with memory).  CPUs or very high
speed adapters would be put on bus that is synchronous with the
memory.

      This method connects CPUs and high speed adapters to a memory
sub-system in a way that performance can scale with the CPU (high
speed adapter) clock rate and will also prevent the additional
latency associated with and asynchronous interface.  At the same
time, this method also has the benefit of having an fixed clock-rate
bus (that is asynchronous to the memory and high speed bus).  Generic
adapters would be put on the fixed clock rate bus.  The generic
adapters would work in all systems while the adapters on the high
speed bus would all need to work at the "high speed" clock.  The high
speed clock would vary from system to system.

      For a coherent system, snoops on the fixed clock bus would need
to be faster that a memory access or a tag directory could be used to
determine if the data is in a cache on the fixed clock bus.  For a
cost reduced system the directory could be removed forcing snoops to
the fixed clock bus on every memory request.  Also, for very high
speed CPUs the high speed bus could be run at a divided clock rate to
maintain a synchronous inte...