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Round-up Anticipator for IEEE Floating Point Standard-754

IP.com Disclosure Number: IPCOM000106187D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 180K

Publishing Venue

IBM

Related People

Atkins, MG: AUTHOR

Abstract

In the IEEE Floating Point Standard-754, three bits are tacked onto the operands - the guard, round and sticky bits (GRS). These bits capture any bits shifted out of an operand in the pre-normalization phase of an adder. The GRS bits are used in the addition. Before leaving the final stage of the adder the GRS bits are truncated. Depending on the rounding method chosen by the user, the resulting state of the GRS bits can cause the final result to be rounded up (incremented), or they can merely be truncated.

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Round-up Anticipator for IEEE Floating Point Standard-754

      In the IEEE Floating Point Standard-754, three bits are tacked
onto the operands - the guard, round and sticky bits (GRS).  These
bits capture any bits shifted out of an operand in the
pre-normalization phase of an adder.  The GRS bits are used in the
addition.  Before leaving the final stage of the adder the GRS bits
are truncated.  Depending on the rounding method chosen by the user,
the resulting state of the GRS bits can cause the final result to be
rounded up (incremented), or they can merely be truncated.

      The most obvious method for rounding the result of an adder is
to wait until after a post normalization shift is done before
deciding to round up or truncate.  However, because of certain
characteristics of the GRS bits, we know that a round-up will only
occur if the post-normalization shift is one of three shifts: (1)
right shift of one (2) no shift (3) left shift of one.  The proof of
this goes beyond the intended discussion of this paper.

      With the above information in mind, I designed a round-up
anticipator that will calculate the round-up possibility and decide
whether a round-up is required while the post-normalization shift is
occurring.  The round-up decision will chose either the rounded-up
result or the shifted result.  See Fig. 1 for a high-level
description.

Note:  I will use the IEEE Std.  754 Double Format to demonstrate
Note:
Note:
Note:
examples.  With the exception of the number of bits involved, the
method is the same for the Single Format.

In the proposed methodology:

1.  The anticipator is placed in parallel with the post normalization
    shift.  In this way, the round direction and the round-up result
    are calculated before the end of the shift.

2.  The final result is chosen according to the round direction.

    o   Truncate - choose the shifter result.

    o   Round-up - choose the increment anticipate result.

      There are two major parts to the round-up anticipate: (1)
increment anticipate and (2) round direction anticipate.  As stated
in the introduction the anticipates use the knowledge that there are
only three post normalization shifts that may later be rounded-up.

      The increment anticipate waits for the add result and then
calculates an increment on one of the three 53 bit adder results that
may require rounding-up after post normalization.  To do this, a 55
bit (Recall that all examples use Double Format numbers.)  increment
is performed on the following bit string: .  C,A0...A53; where C is
the carry out of the adder result and A is the adder result.  See
Fig. 2 for a diagram of the increment anticipator.  The incrementer
shown is for illustration purposes.  One must perform logic
partitioning and reduction to take full advantage of whatever
technology is being used.

There are three stages to the increment:

1.  Calculate the carry in for each bit.
2.  Inver...