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Browse Prior Art Database

Event Tracer to Verify Processor Design Features that are Below the Architectural Level

IP.com Disclosure Number: IPCOM000106205D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 89K

Publishing Venue

IBM

Related People

Vaden, MT: AUTHOR

Abstract

Existing methodology does not verify design operation for certain architecturally transparent features (such as the translation look-aside buffer operation).

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Event Tracer to Verify Processor Design Features that are Below the Architectural Level

      Existing methodology does not verify design operation for
certain architecturally transparent features (such as the translation
look-aside buffer operation).

      Certain features of a processor design are not visible at the
architectural level.  Existing verification methodology does not
check some of these architecturally transparent features.
Specifically, this new technique was developed to aid in the
verification of the translation look-aside buffer (TLB) logic.  By
using a program that detects and logs events, there is an ability to
verify that entries in the TLB were loaded at the right time and
place, were replaced correctly, and that the TLB sharing between I/O
and main memory entries were handled correctly.

      The event trace methodology is used to verify some of the TLB
operations that are not being verified via existing test
methodologies.  The following features are verified:

1.    the correct TLB side was loaded;
2.    the TLB reference was a 'hit' when expected and a 'miss' when
          expected;
3.    the replacement algorithm;
4.    the interaction between I/O and main memory entries.

      The existing test case methodology supports writing programs
that run in simulation on the processor model.  It also supports
writing programs that can monitor the design for certain events.
This, however, is not enough.

      There is a need to know that sequences of events happened in a
specific order.  Consider a program that has 2 loads to the same page
of main memory.  The processor should load the TLB on the access of
the first load, and on the second access merely reference the TLB for
the correct transaction.  If the design was not correctly loading the
TLB, perhaps every reference would cause a reload of the TLB which
would be a major performance problem.

      The event trace method allows monitoring of these types of
sequences.  Test cases using the event tr...