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False Lock Avoidance in Direct Channel Optical Pulse Width Modulator Channel with Method to Increase Phase Error Sampling Rate

IP.com Disclosure Number: IPCOM000106207D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 6 page(s) / 149K

Publishing Venue

IBM

Related People

Chew, KK: AUTHOR

Abstract

Optical DC PWM tracking threshold using a single Phase Locked Loop (PLL) has a tendency to lock to a wrong threshold when the relative phase errors are derived from a clock running at the same frequency as the channel bit frequency. False threshold lock during acquisition can be eliminated by dividing the clock so that it runs at the same frequency as the preamble data pattern. Further, bandwidths in the PLL and threshold tracking system of a DC channel are limited by the phase error sampling rate. Using multiple thresholds increases the phase error sampling rate in a DC channel. A lower synchronization time is therefore possible, eliminating the need for a longer VFO region in the media.

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False Lock Avoidance in Direct Channel Optical Pulse Width Modulator Channel with Method to Increase Phase Error Sampling Rate

      Optical DC PWM tracking threshold using a single Phase Locked
Loop (PLL) has a tendency to lock to a wrong threshold when the
relative phase errors are derived from a clock running at the same
frequency as the channel bit frequency.  False threshold lock during
acquisition can be eliminated by dividing the clock so that it runs
at the same frequency as the preamble data pattern.  Further,
bandwidths in the PLL and threshold tracking system of a DC channel
are limited by the phase error sampling rate.  Using multiple
thresholds increases the phase error sampling rate in a DC channel.
A lower synchronization time is therefore possible, eliminating the
need for a longer VFO region in the media.

      Fig. 1 is a simplified block diagram model of the PLL and
threshold tracking system in a DC channel.  Sign changes happen at
every change in sign in the slope of the analog waveform.  The
following examples are for (2,7) encoding.

      During preamble in a (d,k) RLL single threshold DC channel, the
phase errors are sampled at approximately (d+1)T secs.  The sampling
nature of the phase error measurement places an upper limit on the
achievable bandwidth.  The average sampling rate can be increased by
incorporating multiple thresholds, reducing the phase lag due to
sampling in the system.

      Figs. 2 (a,b,c) illustrate the concept of multiple thresholds
with 2 additional thresholds placed at +/-pi radians apart from the
usual single threshold.  The phase error is measured based on the
relative phase difference between the edges of a comparator output
(between each threshold and the analog signal) and a divided clock
...