Browse Prior Art Database

Staggered Refresh Memory for Personal Computer Systems

IP.com Disclosure Number: IPCOM000106219D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 113K

Publishing Venue

IBM

Related People

Aldereguia, AA: AUTHOR [+5]

Abstract

Described is an architectural implementation that provides the ability to stagger the refresh operation of semiconductor memory devices, as used in large memory personal computer (PC) systems. The staggered refreshing of memory is designed to reduce the instantaneous load on power supplies, thereby reducing power supply size requirements.

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Staggered Refresh Memory for Personal Computer Systems

      Described is an architectural implementation that provides the
ability to stagger the refresh operation of semiconductor memory
devices, as used in large memory personal computer (PC) systems.  The
staggered refreshing of memory is designed to reduce the
instantaneous load on power supplies, thereby reducing power supply
size requirements.

      PC systems are typically designed to support large memory
devices, such as the 256 MB single in-line memory module (SIMM)
mounted on a planar board.  As the size of memory devices increase
within a PC, refresh cycles require increasingly larger current
drains from power supplies.  Although the refresh cycles typically
occur only every fifteen micro-seconds, the system must be designed
to accommodate a current surge during the worst conditions.  As the
current surge increases, the electrical noise throughout the system
also increases.  As a result, the large memory systems required
larger power supplies to accommodate the required refreshing of the
SIMMs, or extensive decoupling of the memory devices during refresh
operations had to be designed within the logic in order to limit the
current surge from the power supplies.

      Generally, the direct memory access (DMA) logic device
incorporates counters which can be programmed to providevarious
refresh rates.  The memory controller, when it receives a refresh
request from the DMA, performs a refresh cycle to the planar memory.
In prior art, PC systems which support an encoded interface between
the memory controller and the memory redrive logic, the timing for
non-refresh cycles was typically provided by the memory controller,
such as through row address strobe (RAS) Enable 1 and decoded from
the Bank Selects (0:2).  Fo...