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Enhanced Dynamic Address Translation for Multi-Addressed Operands

IP.com Disclosure Number: IPCOM000106221D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 133K

Publishing Venue

IBM

Related People

Alpert, AI: AUTHOR [+3]

Abstract

Disclosed is a method, related to the International Business Machines (IBM) Enterprise Systems Architecture / System 390 (ESA/390) Dynamic Address Translation (DAT) process, which provides atomic updates across multiple storage locations.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 46% of the total text.

Enhanced Dynamic Address Translation for Multi-Addressed Operands

      Disclosed is a method, related to the International Business
Machines (IBM) Enterprise Systems Architecture / System 390 (ESA/390)
Dynamic Address Translation (DAT) process, which provides atomic
updates across multiple storage locations.

The method allows programs to redefine existing data or create
multiple data definitions, and allows the hardware to preserve
consistency and integrity across the multiple data definitions.  By
"mirroring" data across multiple storage locations, this enhancement
enables new software to remove itself from dependencies on existing
data structures.

The architecture to support this DAT enhancement are:

o   A new field in the Page-Table Entry (PGTE.X).

        PGTE.X    Indicates whether (PGTE.X = 1) or not (PGTE.X = 0)
    this page
                  contains data defined across multiple storage
    locations.

o   A new control register, DAT Control Register (DCR), containing
    the
        following:

        DCR.E     When one, Enhanced DAT is enabled.

        DCR.F     Indicates whether (DCR.F = 0) or not (DCR.F = 1)
    this is the
                  first DAT performed on an operand defined across
    multiple
                  storage locations.  This field is used to identify
    the initial
                  virtual address (IVA), which is used to determine
    end of
                  (recursive) enhanced DAT.  Note that the virtual
    addresses in
                  the SMATT are mapped 1-1 such that for two
    addresses there
                  would be two entries (V1-V2, V2-V1), for three
    addresses, three
                  entries (V1-V2, V2-V3, V3-V1), and so forth.

        DCR.U     When one, Enhanced DAT is required since the
    storage access is
                  associated with a store or update operation.  When
    zero,

                  Enhanced DAT is not performed since there is no
    change to
                  stored data.

o   A new DAT translation descriptor (DTD).  There is a single DTD
    for the
        system, comprised of the following:

        DTO       DAT Translate-Table Origin.  Bits 1-19 of the DTD,
    with 12
                  zeros appended on the right, form the address that
    designates
                  the beginning of the Multi-Address Translate-Table
    (MATT).

        DTL       DAT Translate-Table Length.  Bits 25-31 of the DTD
    specify the
                  length of the Multi-Address Translate-Table (MATT)
    in units of
                  64 bytes, thus making the length of th...