Browse Prior Art Database

Mapping Physical Nets to Electrical Models

IP.com Disclosure Number: IPCOM000106231D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 118K

Publishing Venue

IBM

Related People

Basile, JE: AUTHOR [+4]

Abstract

This disclosure describes a simple and efficient manner of determining which edges in the physical implementation of a net must be considered lump sum capacitances (drop off) and which must be transmission line. This information can then be used to map the wires in the physical representation of the net to the edges in the electrical model for timing and verification purposes.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Mapping Physical Nets to Electrical Models

      This disclosure describes a simple and efficient manner of
determining which edges in the physical implementation of a net must
be considered lump sum capacitances (drop off) and which must be
transmission line.  This information can then be used to map the
wires in the physical representation of the net to the edges in the
electrical model for timing and verification purposes.

      Part of the design process for higher level packages (e.g.,
TCM, board) is to map a physical implementation of a net to an
electrical model.  This is done for electrical and delay purposes in
order to provide fast analysis of nets without having to employ
detailed circuit analysis tools.  The electrical model is composed of
a set of connection between the driver and receiver pins.  This set
of connections can be viewed as edges, and the pins as nodes.

      The physical implementation of the net varies from the
electrical model in that connections aren't always made at pins.
Connections not made at pins are referred to as a t-junctions (Fig.
1).

      The edges in the electrical model are treated as transmission
line.  The edges in the physical implementation that aren't in the
electrical model are treated as lump sum capacitances and can be
associated with the driver and receiver pins.

      A cluster point is either a driver pin with two or more edges
associated with it, or a receiver pin with three or more edges
associated with it.  The current methodology permits no more than one
cluster point in the electrical model (Fig. 2).

      The points in the physical representation of a net where
connections are made between more than two edges and there is no pin
are called t-junctions.  Since the t-junctions do not appear in the
electrical model of the net, some edges connected to them must be
treated as lump sum capacitances associated with the driver or
receiver pins in order to map the net into the electrical models
(Fig. 2).

      The algorithm used to determine which edges in the physical
implemenation should be treated as transmission line or lump sum
capacitance is based on the following:

1.  Other than the cluster point, the number of edges connected to a
    driver can be no more than one, and the number of edges connected
    to a receiver can be no more than two.  (This is referred to as
    the electrical degree in the electrical model.)

2.  The locations of the driver and receivers are fixed prior to
    physicalwiring so each driver and receiver p is uniquely
    identified with a point p' in the physical implementation of the
    net (i.e., p and p' have the same coordinates).

3.  The degree of the electrical point p, (E(p)), is greater or equal
    to the degree of the physical point p', (P(p')).

4.  Based on 1) and 3) there are on...