Browse Prior Art Database

Method of Providing a Memory-to-Memory Transfer Burst Control for Personal Computers

IP.com Disclosure Number: IPCOM000106235D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Boury, BF: AUTHOR [+4]

Abstract

Described is an architectural implementation for personal computers equipped with a MICRO CHANNEL* (MC) facility to have the ability to providedirect memory access (DMA) memory to memory transfer burst control.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 74% of the total text.

Method of Providing a Memory-to-Memory Transfer Burst Control for Personal Computers

      Described is an architectural implementation for personal
computers equipped with a MICRO CHANNEL* (MC) facility to have the
ability to providedirect memory access (DMA) memory to memory
transfer burst control.

      Devices which utilize the MC facility typically use the BURST
signal to perform multiple transfers during a grant cycle.  Since DMA
memory slaves do not drive this signal, the concept described herein
provides internal logic to generate a BURST signal to the DMA.
During memory to memory transfers,an internal BURST signal is
generated and is dependent on the first-in-first-out (FIFO) enable
bit in the mode register.  When the FIFO is enabled, theinternal
BURST line will be driven active as long as PREEMPTIN is inactive.

      The internal BURST line acts just like the external BURST input
and allows the DMA to do an unlimited amount of transfers as long as
no other devices require the bus.  This allows the memory to memory
transfer to dynamically change the amount of bus allocation based on
the needs of system devices.  The internal BURST also makes the soft
requestlocal arbiter eligible for the hogpen, if fairness is enabled.

      When the FIFO is disabled, an internal BURST is not generated
and the DMA will do a single memory to memory transfer and then
release the bus.  This can be used to limit the memory to memory bus
allocation so as not to s...