Browse Prior Art Database

Bus Allocation Algorithm for Personal Computers

IP.com Disclosure Number: IPCOM000106241D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 102K

Publishing Venue

IBM

Related People

Boury, BF: AUTHOR [+4]

Abstract

Described is an architectural implementation for personal computers equipped with a MICRO CHANNEL* (MC) facility to provide a bus allocation algorithm so as to increase central processing unit (CPU) performance.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Bus Allocation Algorithm for Personal Computers

      Described is an architectural implementation for personal
computers equipped with a MICRO CHANNEL* (MC) facility to provide a
bus allocation algorithm so as to increase central processing unit
(CPU) performance.

      Typically, arbitration for the bus requires the use of central
arbitration control point (CACP) logic whereby a bit is located at an
input/output (I/O) address and is used to instruct the CACP whether
the CPU should be allocated the bus time during arbitration.  This
bit enables the CACP to allocate the bus to the CPU during
arbitration cycles.  When operating under the arbitration enabled
mode, the CACP logic would give the CPU the bus during every
arbitration cycle whether it required it or not.  After giving the
bus to the CPU, the CACP had no way of controlling how much bus time
to allocate to the CPU.  The minimum time that the CPU would own the
bus was the minimum amount of time required to complete the HOLD/HLDA
handshake.  This lack of control of bus time allocation was evident
when a system was loaded with many devices competing for the bus.
The CPU was given only a short period of time during arbitration to
execute instructions while external bursting devices were using
longer periods of time during the grant cycle.  This condition
decreased CPU performance.

      The concept described herein implements an algorithm within the
CACP logic for allocating the bus during arbitration.  The algorithm
allows for varying degrees of CPU bus ownership based on whether the
CPU is bus preempted during three conditions:  the previous grant,
two internal programmable timers and the possibility of a refresh
occurring during the arbitration.  Refresh has priority over the CPU
and becomes a consideration if a refresh cycle occurs and takes
longer than the programmed arbitration cycle length.  This
versatility allows the CACP to be efficient in either a single bus or
a dual bus environment.

      The Table shows the algorithm allocation used during
arbitration.  The CPU is considered to own the bus whenever HOLD = 0.

      By programming a value greater than 0 in the CPU throttle
register, the CPU can be guaranteed to get the bus during every
arbitration cycle whether it requests i...