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Browse Prior Art Database

Program for Verification of Gate Array Scan String

IP.com Disclosure Number: IPCOM000106247D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 135K

Publishing Venue

IBM

Related People

Vaden, MT: AUTHOR

Abstract

This tool provides an automated method of checking the scan string connections in a large gate array, and it provides a file which lists (in scan order) all of the latches in the scan string and the corresponding position in the scan string. This information was previously obtained through a tedious manual analysis of the design. Since the design changes frequently during the development process, the program saves time and guarantees the integrity of the gate array scan string.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Program for Verification of Gate Array Scan String

      This tool provides an automated method of checking the scan
string connections in a large gate array, and it provides a file
which lists (in scan order) all of the latches in the scan string and
the corresponding position in the scan string.  This information was
previously obtained through a tedious manual analysis of the design.
Since the design changes frequently during the development process,
the program saves time and guarantees the integrity of the gate array
scan string.

      This tool was developed as part of a single chip processor
design effort.  It is modelled after the 'Verify' program which works
on chips designed with devices from the ACMOS technology library.

      Description of Invention - this tool is used to guarantee that
the scan string implementation of a large gate array is correct.  It
does this by parsing the design input files for all of the scan
latches, and building an ordered list of the latches found.  The
resulting list can be examined for errors, such as:  latches not
connected and broken scan strings.  This tool is valuable because it
provides a quick way of examining the design for such errors, and it
generates an ordered list of all of the latches in the chip which is
used during various tests.  Existing tools that would normally be
used to do this function did not support the specifics of the gate
array implementation.

      The chip being developed used the LSSD (level sensitive scan
design) methodology.  This methodology allows one to do extensive
debug and testing of the chip.  As part of the methodology, all of
the latches in the chip are connected into one or more serial strings
of latches while in test mode.  (Fig. 1)  In order to test with this
methodology, one must know where each latch is located in the long
scan string.  This scan string verification program automatically
checks for proper scan string connections, and it generates an
ordered list of latches.

      The program works in 2 stages.  The first stage searches the
design files to determine what latches are in the design.  For each
latch found, the following information is extracted and saved into an
in...