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Self-Priming Synchronizing Queue with Deskewing Input Buffer

IP.com Disclosure Number: IPCOM000106258D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 81K

Publishing Venue

IBM

Related People

Garcia, E: AUTHOR

Abstract

Disclosed is a logic circuit which asynchronously receives and synchronizes high speed bytes of digital data. By utilizing a unique self-priming queuing scheme in conjunction with an input deskewing buffer performance and ease of use are optimized.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 53% of the total text.

Self-Priming Synchronizing Queue with Deskewing Input Buffer

      Disclosed is a logic circuit which asynchronously receives and
synchronizes high speed bytes of digital data.  By utilizing a unique
self-priming queuing scheme in conjunction with an input deskewing
buffer performance and ease of use are optimized.

      The circuit is comprised of the following elements which are
depicted in Fig. 1:

1.  An edge triggered input Deskew Register.

2.  A Register Stack comprised of polarity hold (transparent)
    registers.  The actual number of register required is dependent
    on the frequency of data in and data out.

3.  An Empty/Full Status Register implemented with set/reset latches
    - one bit per register in the Register stack.

4.  An edge triggered Ring Counter with a single bit implemented for
    each register in the Register Stack.

5.  A polarity hold Sync-up Register used for synchronizing the
    Empty/Full Status Register to the new timing reference.

6.  A polarity hold Binary Counter.

7.  A Compare circuit.

      The circuit receives data based on the timing and protocol
depicted in Fig. 2 where each byte of data is accompanied by a timing
strobe.

      Each bit of the ring counter controls the clock to an
individual register in the register stack.  Initially the ring
counter is seeded with a single bit active such that last stack
register's clock is held active.  At the falling edge of the first
strobe data is latched into the deskew register, the ring counter is
shifted, and the first bit of the empty/full register is set active.
At this point the ring counter is holding the clock to the first
stack register active allowing it to transparently pass the data
contained in the deskew register to data out multiplexer.  Initial...