Browse Prior Art Database

High Utilization Bi-directional Storage Bus for a Vector Processor

IP.com Disclosure Number: IPCOM000106284D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 69K

Publishing Venue

IBM

Related People

Byrne, CM: AUTHOR [+3]

Abstract

A method for controlling bi-directional data buses toachieve high data throughput and high bus utilization to a vector processor is disclosed. Control of the bi-directional bus is based on the addressing pattern (stride), the type of operation (fetch or store), and the presence or absence of the data in the processor high speed buffer (cache).

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High Utilization Bi-directional Storage Bus for a Vector Processor

      A method for controlling bi-directional data buses toachieve
high data throughput and high bus utilization to a vector processor
is disclosed.  Control of the bi-directional bus is based on the
addressing pattern (stride), the type of operation (fetch or store),
and the presence or absence of the data in the processor high speed
buffer (cache).

      A bi-directional bus shared between fetches and stores is often
used to provide more bandwidth for a smaller hardware cost.  High bus
utilization is achieved by this new method, by assigning the
bi-directional bus to the direction that will maximize overall
throughput across all of the buses.  This high bus utilization
reduces the amount of time a vector instruction takes to complete its
storage operations.

      As an example, the processor is connected to system storage via
three doubleword busses.  A fetch only bus, a store only bus, and a
shared bi-directional bus.  This structure allows a concurrent QW
fetch and a DW store, but not a concurrent QW fetch and a QW store.

      The method of controlling the storage buses consists of two
major items.  First is to bury some of the bi-directional bus turn
around time for vector quadword storage updates.  Second, to deal
with the cases where the vector instruction stream requires
simultaneous fetch and store QW transfers.

      The technology restrictions on bi-directional drivers require
that both drivers cannot be driving the bus at the same time.
Therefore, there is a turn around time during which the
bi-directional...