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Multilayer Circuit Fabrication using Double Exposure of Positive Resist

IP.com Disclosure Number: IPCOM000106294D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Murakami, T: AUTHOR

Abstract

Disclosed is a fabrication method for a build-up type multilayer printed circuit board with pillar connections. Positive resist is utilized twice for patter plating and pillar formation.

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Multilayer Circuit Fabrication using Double Exposure of Positive Resist

      Disclosed is a fabrication method for a build-up type
multilayer printed circuit board with pillar connections.  Positive
resist is utilized twice for patter plating and pillar formation.

The process is performed in the following manner:

o   Positive resist 2 is applied on thin metal layer 1 and patterned
    by selective exposure and development such that openings 3 are
    formed at the regions where pillars or studs are to be formed.

o   Pillars 4 are formed by electroplating.

o   The resist 2 is again selectively exposed and developed to define
    the regions where wiring pattern is to be formed.

o   Electroplating is performed to form wiring conductors 5.  During
    the plating, the height of the pillar 4 increases.

o   The remaining resist is stripped.

o   Fluch etching is performed to remove those portions of the metal
    layer 1 at which the plated conductors 5 do not exist.

o   Resin insulator 6 is applied and polished to provide a flattened
    top surface 7.

o   Thin metal layer 8 is applied and the above steps are repeated,
    if required.